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distinguishing features single-chip composite/s-video ntsc/pal to ycrcb digitizer on-chip ultralock tm square pixel and ccir601 resolu- tion for ntsc and pal chroma comb filtering arbitrary horizontal scaling and vertical scaling (using line store) arbitrary temporal decimation for a reduced frame-rate video sequence programmable hue, brightness, saturation, and contrast user-programmable cropping of the video window 2x oversampling to simplify external analog filtering two-wire i 2 c bus interface on-chip 40-pixel-deep asynchronous output fifo 8- or 16-bit pixel interface ycrcb (4:2:2) output format software selectable three-input analog mux auto ntsc/pal format detect automatic gain control ieee 1149.1 (jtag) interface 100-pin pqfp and tqfp packages related products bt812, bt858, bt855, bt856, bt857 bt851 applications multimedia image processing desktop video video phone teleconferencing interactive video bt819a ?video capture processor for tv/vcr analog input bt817a ?composite video and s-video decoder bt815a ?composite video decoder the bt819a, bt817a and bt815a videostream decoders are a family of single- chip, pin and register compatible, composite ntsc/pal video and s-video decoders. low operating power consumption and power down capability make them ideal low-cost solutions for pc video capture applications on both desktop and portable system platforms. they support square pixel and ccir601 resolu- tions for both ntsc and pal. they have a ?xible pixel port which supports a variety of system interface con?urations, and they are offered in both a 100-pin pqfp and 100-pin tqfp. functional block diagram adc u ltralock tm and c lock mux0 mux1 muxout syncdet refout yref+ yin 16 d ecimation lpf o utput l uma -c hroma s eparation and c hroma o utput v ideo yref fifo and o utput f ormatting a nalog m ux adc cref+ cin cref agc t iming c ontrol d ata i 2 c jtag d emodulation s patial and t emporal s caling v ideo t iming u nit g eneration xt0 xt1 40 mh z 40 mh z mux2 videostream decoders bt819a/817a/815a
copyright ?1996 rockwell semiconductor systems. all rights reserved. print date: september, 1996 rockwell reserves the right to make changes to its products or speci?ations to improve performance, reliability, or manufacturability. information furnished by rockwell semiconductor systems is believed to be accurate and reliable. however, no responsibility is assumed by rockwell semiconductor systems for its use; nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by its implication or otherwise under any patent or patent r ights of rockwell semiconductor systems. rockwell products are not designed or intended for use in life support appliances, devices, or systems where malfunction of a rockwell product can reasonably be expected to result in personal injury or death. rockwell customers using or selling rockwell products for use in such applications do so at their own risk and agree to fully indemnify rockwell for any damages resulting f rom such improper use or sale. bt is a registered trademark of rockwell semiconductor systems. product names or services listed in this publication are for identi?ation purposes only, and may be trademarks or registered trademarks of their respective companies. all other marks mentioned herein are the property of their respective holders. speci?ations are subject to change without notice. printed in the united states of america model number package ambient temperature range BT819AKPF 100-pin pqfp 0?c to +70?c bt819aktf 100-pin tqfp 0?c to +70?c bt817akpf 100-pin pqfp 0?c to +70?c bt817aktf 100-pin tqfp 0?c to +70?c bt815akpf 100-pin pqfp 0?c to +70?c ordering information
iii t able of c ontents list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 bt819a video capture processor for tv/vcr analog input. . . . . . . . . . . . . . . . . . . . 1 bt817a composite/s-video decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 bt815a composite video decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 bt819a architecture and partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ultralock ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 scaling and cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 input interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 output interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 ultralock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 the challenge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 operation principles of ultralock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 y/c separation and chroma demodulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 video scaling, cropping, and temporal decimation . . . . . . . . . . . . . . . . . . . . . . . . . . 19 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 horizontal and vertical scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 luminance scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 chrominance scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 scaling registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 image cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 cropping registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 temporal decimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 video adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 the hue adjust register (hue) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 the contrast adjust register (contrast) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 the saturation adjust registers (sat_u, sat_v) . . . . . . . . . . . . . . . . . . . . . . . . . . 29 the brightness register (bright) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
iv bt819a/7a/5a electrical interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 input interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 analog signal selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 multiplexer considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 autodetection of ntsc or pal video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 flash a/d converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 a/d clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 automatic gain controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 crystal inputs and clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2x oversampling and input filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 output interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 output interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 ycrcb pixel stream format, spi mode 8- and 16-bit formats. . . . . . . . . . . . . . . . . 37 synchronous pixel interface (spi, mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 synchronous pixel interface (spi, mode 2, bytestream) . . . . . . . . . . . . . . . . . . . . . 40 ccir 601 compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 asynchronous pixel interface (api) (bt819a only) . . . . . . . . . . . . . . . . . . . . . . . . . . 45 mode a: fifo controlled by bt819a (bt819a only) . . . . . . . . . . . . . . . . . . . . . . . . . 45 mode b: fifo controlled by system (bt819a only) . . . . . . . . . . . . . . . . . . . . . . . . . 46 asynchronous pixel interface control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 starting and stopping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 addressing the bt819a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 reading and writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 need for functional veri?ation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 jtag approach to testability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 optional device id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 veri?ation with the tap controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 pc board layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 ground planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 power planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 digital signal interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 analog signal interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 latch-up avoidance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
v bt819a/7a/5a control register de?itions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 0x00 ?device status register (status) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 0x01 ?input format register (iform) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 0x02 ?temporal decimation register (tdec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 0x03 ?msb cropping register (crop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 0x04 ?vertical delay register, lower byte (vdelay_lo) . . . . . . . . . . . . . . . . . . . . 72 0x05 ?vertical active register, lower byte (vactive_lo) . . . . . . . . . . . . . . . . . . 73 0x06 ?horizontal delay register, lower byte (hdelay_lo) . . . . . . . . . . . . . . . . . 73 0x07 ?horizontal active register, lower byte (hactive_lo) . . . . . . . . . . . . . . . . 73 0x08 ?horizontal scaling register, upper byte (hscale_hi) . . . . . . . . . . . . . . . . 74 0x09 ?horizontal scaling register, lower byte (hscale_lo) . . . . . . . . . . . . . . . 74 0x0a ?brightness control register (bright) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 0x0b ?miscellaneous control register (control) . . . . . . . . . . . . . . . . . . . . . . . . . 76 0x0c ?luma gain register, lower byte (contrast_lo) . . . . . . . . . . . . . . . . . . . 77 0x0d ?chroma (u) gain register, lower byte (sat_u_lo) . . . . . . . . . . . . . . . . . . 78 0x0e ?chroma (v) gain register, lower byte (sat_v_lo) . . . . . . . . . . . . . . . . . . 79 0x0f ?hue control register (hue) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 0x10 ?reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 0x11 ?reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 0x12 ?output format register (oform) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 0x13 ?vertical scaling register, upper byte (vscale_hi) . . . . . . . . . . . . . . . . . . . 84 0x14 ?vertical scaling register, lower byte (vscale_lo) . . . . . . . . . . . . . . . . . . 85 0x15 ?test control register (test) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 0x16 ?video timing polarity register (vpole) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 0x17 ?id code register (idcode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 0x18 ?agc delay register (adelay) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 0x19 ?burst delay register (bdelay) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 0x1a ?adc interface register (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 0x1b to 0x1e ?reserved registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 0x1f ?software reset register (sreset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
vi bt819a/7a/5a parametric information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 dc electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 ac electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 package mechanical drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 datasheet revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
vii l ist of f igures bt819a/7a/5a list of figures figure 1. bt819a/7a/5a detailed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. bt819a pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 3. bt817a pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 4. bt815a pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5. ultralock behavior for ntsc square pixel output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 6. y/c separation and chroma demodulation for composite video. . . . . . . . . . . . . . . . . . 17 figure 7. y/c separation filter responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 figure 8. combined luma notch and optional luma 3 mhz low pass filter response . . . . . . . 18 figure 9. optional luma 3 mhz low pass filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 10. combined luma notch, optional luma 3 mhz low pass, and oversampling filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11. combined luma notch and oversampling filter response . . . . . . . . . . . . . . . . . . . . . . 20 figure 12. filtering and scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 13. effect of the cropping and active registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 14. regions of the video signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 15. typical external circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 16. clock options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 17. luma & chroma 2x oversampling filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 18. output mode summary (api mode only for bt819a) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 19. ycrcb 4:2:2 pixel stream format (spi mode, 8 and16 bits) . . . . . . . . . . . . . . . . . . . . . 38 figure 20. bt819a, bt817a, bt815a synchronous pixel interface, mode 1 (spi-1) . . . . . . . . . . . . . 39 figure 21. basic timing relationships for spi mode 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 22. data output in spi mode 2 (bytestream) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 23. video timing in spi modes 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 24. horizontal timing signals in the spi modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
viii l ist of f igures bt819a/7a/5a figure 25. asynchronous pixel interface (api) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 26. basic timing relationships for api mode a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 27. api-a datastream during a field transition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 28. basic timing relationships for api mode b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 29. the relationship between scl and sda . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 30. i 2 c slave address con?uration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 31. i 2 c protocol diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 32. instruction register (ir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 33. example ground plane layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 34. optional regulator circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 35. typical power and ground connection diagram and parts list. . . . . . . . . . . . . . . . . . . . 64 figure 36. example schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 37. clock timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 38. output enable timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 39. jtag timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 40. fifo output timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 41. 100pqfp package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 42. 100tqfp package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
ix l ist of t ables bt819a/7a/5a list of tables table 1. videostream feature options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin descriptions grouped by pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. scaling ratios for popular formats using frequency values . . . . . . . . . . . . . . . . . . . . . . 24 table 4. pixel/pin map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 5. description of the control codes in the pixel stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 6. data output ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 7. synchronous pixel interface (spi) control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 8. operation of timing signals, api (both modes a and b) . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 9. asynchronous pixel interface control signals, bt819a only . . . . . . . . . . . . . . . . . . . . . . 50 table 10. bt819a address matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 11. example i 2 c data transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 12. bt819a boundary scan register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 13. device identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 14. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 15. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 16. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 17. clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 18. power supply current parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 19. output enable timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 20. jtag timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 21. fifo timing parameters (bt819a only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 22. decoder performance parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 23. bt819a datasheet revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
1 f unctional d escription functional overview brooktrees videostream products are a family of single-chip, pin and register compatible solutions for processing analog ntsc/pal video into digital 4:2:2 ycrcb video. they provide a comprehensive choice of capabilities to enable the feature set and cost to be tailored to different system hardware con?urations. all solutions are housed in a 100-pin qfp package. a detailed block diagram is shown in figure 1. bt819a video capture processor for tv/vcr analog input the bt819a video capture processor is a fully integrated single-chip decoding and scaling solution for analog ntsc/pal input signals from tv tuners, vcrs, cameras, and other sources of composite or y/c video. it is the ?st front-end input solution for low-cost pc video/graphics systems to deliver complete integration and high-performance video synchronization, y/c separation, ?tered scaling and optional fifoed output pixel data. the bt819a has all the mixed signal and dsp circuitry required to convert an analog composite waveform into a scaled digital video stream supporting a variety of video formats, resolutions and frame rates. bt817a composite/s-video decoder the bt817a provides full composite and s-video capability along with ?tered horizontal scaling. however, vertical scaling can be implemented by line-dropping only, and there is no output fifo option. bt815a composite video decoder the bt815a has the minimum feature set with composite-only video decoding (no s-video capability). as with the bt817a, vertical scaling is implemented through line dropping, and there is no output fifo option. see table 1 for a comparison of bt819a, bt817a and bt815a features. table 1. videostream feature options feature options bt819a bt817a bt815a composite video decoding 333 s-video decoding 33 filtered vertical scaling 3 optional output fifo 3
2 f unctional d escription functional overview bt819a/7a/5a the synchronous pixel interface (non-fifoed output) is common to all three pin-compatible devices, which enables a single system hardware design to be used for all three. similarly, a common i 2 c register set allows a single piece of driver code to be written for software control of all three options. bt819a architecture and partitioning the bt819a has been developed to provide the most cost-effective, high-quality video input solution for low-cost multimedia subsystems that integrate both graph- ics display and video capabilities. the feature set of the bt819a supports a vid- eo/graphics system partitioning which optimizes the total cost of a system con?ured both with and without video capture capabilities. this enables system vendors to easily offer products with various levels of video support using a single base-system design. as graphics chip vendors move from graphics-only to video/graphics coproces- sors and eventually to single-chip video/graphics processor implementations, the ability to ef?iently use silicon and package pins to support both graphics acceler- ation, video playback acceleration and video capture becomes critical. this prob- lem becomes more acute as the race towards higher performance graphics requires more and more package pins to be consumed for wide 64-bit memory interfaces and glueless local bus interfaces. the bt819a minimizes the cost of the video capture function integration in a number of ways. recognizing that ycrcb to rgb color space conversion is be- coming a required feature of multimedia controllers for acceleration of digital vid- eo playback, the bt819a avoids redundant functionality and allows the downstream controller to perform this task. secondly, the bt819a integrates the fifo which would otherwise be dedicated to feeding a live video stream to the di- rect memory access engine (dma) in a video controller. finally, the bt819a can minimize the number of interface pins required by a downstream multimedia con- troller in order to keep package costs to a minimum. controller systems that are designed to take advantage of these features enable video capture capability to be added to the base system in a modular fashion using only a single integrated circuit (ic). the bt817a and bt815a are targeted at system con?urations using stand-alone video controllers or codecs which typically integrate the scaling and video fifo functions. ultralock ? the bt819a, bt817a and bt815a employ a proprietary technique known as ul- tralock to lock to the incoming analog video signal. it will always generate the re- quired number of pixels per line from an analog source in which the line length can vary by as much as a few microseconds. ultralocks digital locking circuitry en- ables the videostream decoders to quickly and accurately lock on to video signals, regardless of their source. since the technique is completely digital, ultralock can recognize unstable signals caused by vcr headswitches or any other deviation and adapt the locking mechanism to accommodate the source. ultralock uses non- linear techniques which are dif?ult, if not impossible, to implement in genlock systems. and unlike linear techniques, it adapts the locking mechanism automati- cally.
3 f unctional d escription functional overview bt819a/7a/5a scaling and cropping the bt819a can reduce the video image size in both horizontal and vertical direc- tions independently using arbitrarily selected scaling ratios. the x and y dimen- sions can be scaled down to one-fourteenth of the full resolution. horizontal scaling is implemented with a six-tap interpolation ?ter while two-tap interpola- tion is used for vertical scaling with a line store. the bt817a and bt815a support vertical scaling by line-dropping. the video image can be arbitrarily cropped by programming the active ?g to reduce the number of active scan lines and active horizontal pixels per line. the bt819a, bt817a and bt815a also support a temporal decimation feature that reduces video bandwidth by allowing frames or ?lds to be dropped from a video sequence at regular but arbitrarily selected intervals. input interface analog video signals are input to the bt819a/7a/5a via a three-input multiplexer that can select between three composite source inputs or between two composite and a single s-video input source. when an s-video source is input to the bt819a, the luma component is fed through the input analog multiplexer, and the chroma component is fed directly into the c input pin (the bt815a does not support s-vid- eo input). an automatic gain control circuit enables the bt819a/7a/5a to compen- sate for reduced amplitude in the analog signal input. the clock signal interface consists of two pairs of pins for crystal connection and two clock output pins. one pair of crystal pins is for connection to a 28.64 mhz (8*ntsc fsc) crystal which is selected for ntsc operation. the other is for pal operation with a 35.47 mhz (8*pal fsc) crystal. either of the two crystal frequencies can be selected to generate clkx1 and clkx2 output signals. clkx2 operates at the full crystal frequency (8*fsc) whereas clkx1 operates at half the crystal frequency (4*fsc). either fundamental or third harmonic crystals may be used. alternatively, cmos oscillators may be used. output interface the bt819as output interface can be set up to support two different con?ura- tions: the synchronous pixel interface (spi) and the asynchronous pixel interface (api). the bt817a and bt815a support the synchronous pixel interface only. both the spi and the api can support a ycrcb 4:2:2 data stream over a 16-bit- wide path. the spi also supports an 8-bit path. when the pixel output port is con- ?ured to operate 8 bits wide, 8 bits of chrominance data are output on the ?st clock cycle followed by 8 bits of luminance data on the next clock cycle for each pixel. two clocks are required to output one pixel in this mode, thus a 2x clock is used to output the data. in spi mode, the bt819a/7a/5a output interface is similar to the bt812 inter- face. the bt819a/7a/5a outputs all horizontal and vertical blanking pixels in ad- dition to the active pixels synchronous with clkx1 (16-bit mode) or clkx2 (8-bit mode). it is also possible to insert control codes into the pixel stream using chrominance and luminance values that are outside the allowable chroma and luma ranges. these control codes can be used to ?g video events such as active, hreset, and vreset. decoding these video events downstream enables the vid-
4 f unctional d escription functional overview bt819a/7a/5a eo controller to do away with pins required for the corresponding video control signals. in the api mode, the bt819a outputs only the active pixels and control codes at a rate asynchronous with the sample clock. a 40-pixel-deep fifo buffers the pixel output port and enables the system to burst pixels out of the bt819a at rates up to 35 mpixels/sec. an input clock must be provided on clkin for operation in this mode. the bt819a outputs the dvalid, aef and aff ?gs to provide the system information on the status of the fifo. i 2 c interface the bt819a/7a/5a registers are accessed via a two-wire inter-integrated circuit (i 2 c) interface. the bt819a/7a/5a operates as a slave device. serial clock and data lines, scl and sda, are used to transfer data from the bus master at a rate of 100 kbits/s. chip select and reset signals are also available to select one of two possible bt819a/7a/5a devices in the same system and to set the registers to their default values.
5 f unctional d escription functional overview bt819a/7a/5a figure 1. bt819a/7a/5a detailed block diagram muxout mux0 mux1 xt1o xt1i xt0o xt0i clkx1 clkx2 rst sda i2ccs scl qclk hreset vreset active field cbflag dvalid v ideo s caling i nput i nterface o utput i nterface y/c s eparation and c hroma d emodulation v ideo i 2 c i nterface frst oe vd[15:8] vd[7:0] clkin rden aff aef syncdet agccap refout yref yin yref+ y adc b ias cref cin cref+ c adc b ias clevel c lock i nterface jtag i nterface and c ropping a djustments c a/d y a/d agc and s ync d etect o versampling l ow -p ass f ilter y/c s eparation c hroma d emod h ue , s aturation , and b rightness a djust h orizontal and v ertical f iltering and s caling 40 p ixel fifo v ideo t iming c ontrol i 2 c c locking jtag tdo tdi tms tck trst (b t 819a/7 o nly ) (b t 819a o nly ) mux2
6 f unctional d escription pin descriptions bt819a/7a/5a pin descriptions pins with alternate de?itions on the bt817a or bt815a are indicated by shading (e.g., see pin number 67). table 2. pin descriptions grouped by pin function (1 of 6) pin # i/o pin name description the input stage pins 55 i mux0 analog composite video inputs to the on-chip input multiplexer. used to select between three composite sources or two composite and one s-video source. unused pins should be connected to gnd. 57 i mux1 45 i mux2 53 o muxout the analog video output of the 3 to 1 multiplexer. connected to the yin pin. 52 i yin the analog composite or luma input to they-adc. 67 i cin the analog chroma input to the c-adc. nc may be left unconnected. 59 i syncdet the sync stripper input used to generate timing information for agc circuit. must be connected through a 0.1 m f capacitor to the same source as the y-adc. a 1 m w bleeder resistor should be connected to ground. 41 a agccap the agc time constant control capacitor node. must be connected to a 0.1 m f capacitor to ground. 43 o refout output of the agc which drives the yref+ and cref+ pins. 49 i yref+ the top of the reference ladder of the y-adc. this should be connected to refout. 62 i yref the bottom of the reference ladder of the y-adc. this should be connected to ana- log ground (agnd). 64 i cref+ the top of the reference ladder of the c-adc. this should be connected to refout. agnd/cref+ may be connected to either agnd or refout. 73 i cref the bottom of the reference ladder of the c-adc. this should be connected to ana- log ground (agnd). g agnd ground for analog circuitry on bt815a. 74 i clevel an input to provide the dc level reference for the c-adc. this voltage should be one half of cref+. agnd/clevel may be connected to either agnd or 1/2 the voltage on cref+ (the same connec- tion as on the bt819a and bt817a.)
7 f unctional d escription pin descriptions bt819a/7a/5a 51 a yabias the y adc bias pins. should be left unconnected. for backward compatibility with the bt819/7/5, these pins may optionally be connected with 0.1 m f capacitors to ground. 46 a ycbias 50 a ydbias 70 a cabias the c adc bias pins. should be left unconnected. for backward compatibility with the bt819/7/5, these pins may optionally be connected with 0.1 m f capacitors to ground. 69 a ccbias 63 a cdbias 70 nc no connect on bt815a. 69 nc 63 nc the i 2 c interface pins 19 i scl the i 2 c serial clock line. 18 i/o sda the i 2 c serial data line. 14 i i2ccs the i 2 c chip select input (ttl compatible). this pin is used to select one of two bt819a devices in the same system. this pin is internally pulled to ground with an effective 18 k w resistance. 15 i rst reset control input (ttl compatible). a logical zero for a minimum of four consecu- tive clock cycles resets the device to its default state. a logical zero for less than eight xtal cycles will leave the device in an undetermined state. table 2. pin descriptions grouped by pin function (2 of 6) pin # i/o pin name description
8 f unctional d escription pin descriptions bt819a/7a/5a the video timing unit pins 82 o hreset horizontal reset output (ttl compatible). this signal indicates the beginning of a new line of video. in spi mode : this signal is 64 clkx1 clock cycles wide. in spi mode, the falling edge of this output indicates the beginning of a new scan line of video. in api mode : this signal is one clock cycle wide and is output relative to clkin. in api mode, it immediately follows the last active pixel of a line. note: the polarity of this pin is programmable through the vpole register. 79 o vreset vertical reset output (ttl compatible). this signal indicates the beginning of a new ?ld of video. in spi mode : this signal is output coincident with the rising edge of clkx1, and is normally six lines wide. the falling edge of vreset indicates the beginning of a new ?ld of video. in api mode : this signal is a one clock cycle wide, active low pulse output rela- tive to clkin. it immediately follows the hreset pixel, and it indicates that the next active pixel is the ?st active pixel of the next ?ld. note: the polarity of this pin is programmable through the vpole register. 83 o active active video output (ttl compatible). this pin is a logical high during the active/viewable periods of the video stream. the active region of the video stream is programmable. note: the polarity of this pin is programmable through the vpole register. 85 i rden asynchronous fifo read enable signal (ttl compatible). a logical high on this pin enables a read from the output fifo. when using the bt819a in spi mode, rden must be pulled low. g gnd ground for digital circuitry on bt817a and bt815a. 94 o qclk quali?d clock output. see ?utput interface on page 37 for a complete descrip- tion of the qclk pin functions. 98 i oe output enable control (ttl compatible). all video timing unit output pins and all clock interface output pins contain valid data following the rising edge of clkin, after oe has been asserted low. the above outputs are three-stated when oe is held high. this function is asynchronous. the three-stated pins include: vd[15:0], hreset , vreset , active, dvalid, cbflag, field, aef, aff, qclk, clkx1, and clkx2. 78 o field odd/even ?ld output (ttl compatible). high state on field pin indicates that an even ?ld is being digitized. note: the polarity of this pin is programmable through the vpole register. 89 o cbflag cb data identi?r (ttl compatible). high state on this pin indicates that vd[7:0] bus contains cb chroma information. note: the polarity of this pin is programmable through the vpole register. table 2. pin descriptions grouped by pin function (3 of 6) pin # i/o pin name description
9 f unctional d escription pin descriptions bt819a/7a/5a 2? o vd[15:8] digitized video data outputs (ttl compatible). vd0 is the least signi?ant bit of the bus in 16-bit mode. vd8 is the least signi?ant bit of the bus in 8-bit mode. in spi mode : the information is output with respect to clkx1 in 16-bit mode, and clkx2 in 8-bit mode. in spi mode 2, this port is con?ured to output control codes as well as data. in api mode : this port may be used only in 16-bit mode with vd0 as the least signi?ant bit. the data is output with respect to clkin. in api mode, control codes for hreset and vreset are always inserted into the data stream. 22?9 o vd[7:0] 84 o dvalid data valid output (ttl compatible). in spi mode : this pin indicates if a valid pixel is being output onto the data bus. the bt819a digitizes video at eight times the subcarrier rate, and outputs scaled video. therefore, there are more clocks than valid data. dvalid indicates when valid pixel data is being output. in api mode : dvalid performs a different function. it toggles high when the fifo has 20 locations ?led, and remains high until the fifo is empty. it can be used to control fifo reads for bursting information out of the fifo. dvalid may be programmed to toggle when almost full (32 pixels). in api mode, dvalid indi- cates valid data in the fifo, which includes both pixel information and control codes. note: the polarity of this pin is programmable through the vpole register. the fifo pins (bt819a only) 87 o aef almost empty flag. indicates when there are less than 9 pixels in the fifo. note: the aef ?g is pipelined to the output of the chip. also, the fifo is being written into during this time. therefore, the actual number of pixels in the fifo when aef toggles will vary. the number of pixels remaining could be as low as 2. the system should stop reading from the fifo as soon as aef indicates almost empty. see figure 28 for a recommended circuit. nc no connect on bt817a and bt815a. 86 o aff almost full flag. indicates when there are more than 32 fifo locations full. it can also be programmed to signal a half full condition (with 20 locations full). note: the polarity of this pin is programmable through the vpole register. nc no connect on bt817a and bt815a. 91 i clkin asynchronous fifo output clock (ttl compatible). this asynchronous clock is used to output data onto the vd15-vd0 bus and other vtu control signals. clkx2 or clkx1 outputs of the bt819a can be tied to this pin. when using the bt819a in spi mode, clkin must be pulled low. g gnd ground for digital circuitry on bt817a and bt815a. 88 i frst fifo reset (ttl compatible). a logical 0 on this pin asynchronously resets the read and write address pointers to zero. when using the bt819a in spi mode, frst must be pulled high. p vdd power supply for digital circuitry on bt817a and bt815a. table 2. pin descriptions grouped by pin function (4 of 6) pin # i/o pin name description
10 f unctional d escription pin descriptions bt819a/7a/5a the clock interface pins 12 a xt0i clock zero pins. a 28.64 mhz (8*fsc) fundamental (or third harmonic) crystal can be tied directly to these pins, or a single-ended oscillator can be connected to xt0i. cmos level inputs must be used. this clock source is selected for ntsc input sources. when the chip is con?ured to decode pal but not ntsc (and therefore only one clock source is needed), the 35.47 mhz source is connected to this port (xt0). 13 a xt0o 16 a xt1i clock one pins. a 35.47 mhz (8*fsc) fundamental (or third harmonic) crystal can be tied directly to these pins, or a single-ended oscillator can be connected to xt1i. cmos level inputs must be used. this clock source is selected for pal input sources. if either ntsc or pal is being decoded, and therefore only xt0i and xt0o are connected to a crystal, xt1i should be tied either high or low, and xt1o must be left ?ating. 17 a xt1o 97 o clkx1 1x clock output (ttl compatible). the frequency of this clock is 4*fsc (14.31818 mhz for ntsc or 17.734475 mhz for pal). 99 o clkx2 2x clock output (ttl compatible). the frequency of this clock is 8*fsc (28.63636 mhz for ntsc, or 35.46895 mhz for pal). 80 i numxtal crystal format pin. this pin is set to indicate whether one or two crystals are present so that the bt819a can select xt1 or xt0 as the default in auto format mode. a logical zero on this pin indicates one crystal is present. a logical one indi- cates two crystals are present. this pin is internally pulled down to ground with an effective 18 k w resistance. the jtag pins 34 i tck test clock (ttl compatible). used to synchronize all jtag test structures. when jtag operations are not being performed, this pin must be driven to a logical low. 36 i tms test mode select (ttl compatible). jtag input pin whose transitions drive the jtag state machine through it sequences. when jtag operations are not being performed, this pin must be left ?ating or tied high. 37 i tdi test data input (ttl compatible). jtag pin used for loading instruction to the tap controller or for loading test vector data for boundary-scan operation. when jtag operations are not being performed, this pin must be left ?ating or tied high. 32 o tdo test data output (ttl compatible). jtag pin used for verifying test results of all jtag sampling operations. this output pin is active for certain jtag operations and will be three-stated at all other times. 35 i trst test reset (ttl compatible). jtag pin used to initialize the jtag controller. this pin is tied low for normal device operation. when pulled high, the jtag controller is ready for device testing. table 2. pin descriptions grouped by pin function (5 of 6) pin # i/o pin name description
11 f unctional d escription pin descriptions bt819a/7a/5a power and ground pins 1, 10, 20, 30, 38, 76, 92, 96 p vdd +5 v power supply for digital circuitry. all vdd pins must be connected together as close to the device as possible. a 0.1 m f ceramic capacitor should be connected between each group of vdd pins and the ground plane as close to the device as possible. 40, 44, 48, 60, 65, 72 p vaa +5 v vpos +5 v power supply for analog circuitry. all vaa pins and vpos must be connected together as close to the device as possible. a 0.1 m f ceramic capacitor should be connected between each group of vaa pins and the ground plane as close to the device as possible. 11, 21, 31, 33, 39, 77, 81, 90, 93, 95, 100 g gnd ground for digital circuitry. all gnd pins must be connected together as close to the device as possible. 81 nc may be left unconnected. 42, 47, 54, 56, 58, 61, 66, 71, 75 g agnd vneg ground for analog circuitry. all agnd pins and vneg must be connected together as close to the device as possible. i/o column legend: i = digital input o = digital output i/o = digital bidirectional a = analog g = ground p = power table 2. pin descriptions grouped by pin function (6 of 6) pin # i/o pin name description
12 f unctional d escription pin assignments bt819a/7a/5a pin assignments figure 2. bt819a pinout notes: (1). alternate pin definitions for bt817a and bt815a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 numxtal vreset field gnd vdd agnd clevel (1) cref (1) vaa agnd cabias (1) ccbias (1) nc cin (1) agnd vaa cref+ (1) cdbias (1) yref agnd vaa syncdet agnd mux1 agnd mux0 agnd muxout yin yabias gnd clkx2 oe clkx1 vdd gnd gnd qclk clkin (1 ) cbflag aef (1) aff (1) rden (1) dvalid active hreset gnd tdo gnd tck trst tms tdi vdd gnd vpos agccap vneg refout vaa mux2 ycbias agnd vaa yref+ ydbias vdd vd15 vd14 vd13 vd12 vd11 vd10 vd9 vd8 vdd gnd vd7 vd6 vd5 vd4 vd3 vd2 vd1 vd0 vdd gnd xt0i xt0o rst xt1i xt1o sda scl i2ccs vdd gnd (1) vdd gnd frst (1) bt819a
13 f unctional d escription pin assignments bt819a/7a/5a figure 3. bt817a pinout notes: (1). alternate pin definitions for bt819a and bt815a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 numxtal vreset field gnd vdd agnd clevel (1) cref (1) vaa agnd cabias (1) ccbias (1) nc cin (1) agnd vaa cref+ (1) cdbias (1) yref agnd vaa syncdet agnd mux1 agnd mux0 agnd muxout yin yabias gnd clkx2 oe clkx1 vdd gnd gnd qclk gnd (1) cbflag nc (1) nc (1) gnd (1) dvalid active hreset gnd tdo gnd tck trst tms tdi vdd gnd vpos agccap vneg refout vaa mux2 ycbias agnd vaa yref+ ydbias vdd vd15 vd14 vd13 vd12 vd11 vd10 vd9 vd8 vdd gnd vd7 vd6 vd5 vd4 vd3 vd2 vd1 vd0 vdd gnd xt0i xt0o rst xt1i xt1o sda scl i2ccs vdd nc (1) vdd gnd vdd (1) bt817a
14 f unctional d escription pin assignments bt819a/7a/5a figure 4. bt815a pinout notes: (1). alternate pin definitions for bt819a and bt817a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 numxtal vreset field gnd vdd agnd agnd/clevel (1) agnd (1) vaa agnd nc (1) nc (1) nc nc (1) agnd vaa agnd/cref+ (1) nc (1) yref agnd vaa syncdet agnd mux1 agnd mux0 agnd muxout yin yabias gnd clkx2 oe clkx1 vdd gnd gnd qclk gnd (1) cbflag nc (1) nc (1) gnd (1) dvalid active hreset gnd tdo gnd tck trst tms tdi vdd gnd vpos agccap vneg refout vaa mux2 ycbias agnd vaa yref+ ydbias vdd vd15 vd14 vd13 vd12 vd11 vd10 vd9 vd8 vdd gnd vd7 vd6 vd5 vd4 vd3 vd2 vd1 vd0 vdd gnd xt0i xt0o rst xt1i xt1o sda scl i2ccs vdd nc (1) vdd gnd vdd (1) bt815a
15 f unctional d escription ultralock bt819a/7a/5a ultralock the challenge the line length (the interval between the midpoints of succeeding horizontal sync pulses) of analog video sources is not constant. for a stable source such as studio quality source or test signal generators, this variation is very small: 2 ns. howev- er, for an unstable source such as a vcr, laser disk player, or tv tuner, line length variation is as much as a few microseconds. digital display systems require a ?ed number of pixels per line despite these variations. the bt819a employs a technique known as ultralock to implement locking to the horizontal sync and the subcarrier of the incoming analog video sig- nal by generating the required number of pixels per line. operation principles of ultralock ultralock is based on sampling using a ?ed-frequency stable clock. since the video line length will vary, the number of samples generated using a ?ed-frequen- cy sample clock will also vary from line to line. if the number of generated samples per line is always greater than the number of samples per line required by the par- ticular video format, the number of acquired samples can be reduced to ? the re- quired number of pixels per line. the bt819a requires an 8*fsc (28.64 mhz for ntsc and 35.47 mhz for pal) crystal or oscillator input signal source. the 8*fsc clock signal, or clkx2, is di- vided down to clkx1 internally (14.32 mhz for ntsc and 17.73 mhz for pal). both clkx2 and clkx1 are made available to the system. ultralock operates at clkx1 although the input waveform is sampled at clkx2 then low pass ?tered and decimated to clkx1 sample rate. at a 4*fsc (clkx1) sample rate there are 910 pixels for ntsc and 1,135 pixels for pal within a nominal line time interval (63.5 m s for ntsc and 64 m s for pal). for square pixel ntsc and pal formats there should only be 780 and 944 pixels per video line, respectively. this is because the square pixel clock rates are slower than a 4*fsc clock rate, i.e., 12.27 mhz for ntsc and 14.75 mhz for pal. ultralock accommodates line length variations from nominal in the incoming video by always acquiring more samples, at an effective 4*fsc rate, than are re- quired by the particular video format and outputting the correct number of pixels per line. ultralock then interpolates the required number of pixels in a way that maintains the stability of the original image despite variation in the line length of the incoming analog waveform. the example illustrated in figure 5 shows three successive lines of video being decoded for square pixel ntsc output. the ?st line is shorter than the nominal ntsc line time interval of 63.5 m s. on this ?st line, a line time of 63.2 m s sampled at 4*fsc (14.32 mhz) generates only 905 pixels. the second line matches the nominal line time of 63.5 m s and provides the expected 910 pixels. finally, the
16 f unctional d escription ultralock bt819a/7a/5a third line is too long at 63.8 m s within which 913 pixels are generated. in all three cases, ultralock sends only 780 pixels through the output fifo. ultralock can be used to extract any programmable number of pixels from the original video stream as long as the sum of the nominal pixel line length (910 for ntsc and 1,135 for pal) and the worst case line length variation from nominal in the active region is greater than or equal to the required number of output pixels per line, i.e., for a description of how the bt819a uses the fifo and the output interface, please see the output interface section in the electrical interfaces chapter. it should be noted that, for stable inputs, ultralock guarantees the time between the falling edges of hreset only to within one pixel. ultralock does, however, guarantee the number of active pixels in a line as long as the above relationship holds. figure 5. ultralock behavior for ntsc square pixel output analog waveform 63.2 ms 63.5 ms 63.8 ms 905 pixels 910 pixels 913 pixels line length pixels per line 780 pixels 780 pixels 780 pixels pixels sent to the fifo by ultralock p nom p var + p desired 3 where: p nom = nominal number of pixels per line at 4*fsc sample rate (910 for ntsc, 1,135 for pal) p var = variation of pixel count from nominal at 4*fsc (can be a positive or negative number) p desired = desired number of output pixels per line
17 f unctional d escription y/c separation and chroma demodulation bt819a/7a/5a y/c separation and chroma demodulation y/c separation and chroma decoding are handled as shown in figure 6. bandpass and notch ?ters are implemented to separate the composite video stream. the ?- ter responses are shown in figure 7. the optional chroma comb ?ter is imple- mented in the vertical scaling block. see the video scaling, cropping, and temporal decimation section in this chapter. figure 6. y/c separation and chroma demodulation for composite video n otch f ilter b and p ass f ilter l ow p ass f ilter l ow p ass f ilter sin cos y q or u i or v c omposite figure 7. y/c separation filter responses ntsc pa l ntsc pa l
18 f unctional d escription y/c separation and chroma demodulation bt819a/7a/5a figure 8 is the combined frequency response of the optional luma 3 mhz low pass ?ter (figure 9 in the video scaling section), and the luma notch ?ter in figure 7. the luma decimation ?ter is typically enabled during scaling to cif res- olution or below. when scaling is not implemented, the luma decimation ?ter will normally be bypassed (optional), providing a luma spectrum as shown in figure 7. figure 8 shows the combined ?ter response of the luma notch, the optional luma 3 mhz low pass and the oversampling ?ters. figure 11 shows the com- bined ?ter response of the luma notch and oversampling ?ters. figure 12 sche- matically describes the ?tering and scaling operations. in addition to the y/c separation and chroma demodulation illustrated in figure 6, the bt819a also supports chrominance comb ?tering as an optional ?- tering stage after chroma demodulation. the chroma demodulation generates baseband i and q (ntsc) or u and v (pal) color difference signals. for s-video operation, the digitized luma data bypasses the y/c separation block completely, and the digitized chrominance is passed directly to the chroma demodulator. for monochrome operation, the y/c separation block is also bypassed, and the saturation registers (sat_u and sat_v) are set to zero. figure 8. combined luma notch and optional luma 3 mhz low pass filter response ntsc pa l
19 f unctional d escription video scaling, cropping, and temporal decimation bt819a/7a/5a video scaling, cropping, and temporal decimation overview the bt819a provides three mechanisms to reduce the amount of video pixel data in its output stream; down-scaling, cropping, and temporal decimation. all three can be controlled independently. figure 9. optional luma 3 mhz low pass filter response ntsc pa l
20 f unctional d escription video scaling, cropping, and temporal decimation bt819a/7a/5a figure 10. combined luma notch, optional luma 3 mhz low pass, and oversampling filter response ntsc pa l c ombined response of filters in figures 7, 9, and 17 figure 11. combined luma notch and oversampling filter response ntsc pa l c ombined response of filters in figures 7 and 17
21 f unctional d escription video scaling, cropping, and temporal decimation bt819a/7a/5a horizontal and vertical scaling the bt819a provides independent and arbitrary horizontal and vertical down scal- ing. the maximum scaling ratio is 14:1 in both x and y dimensions. the different methods utilized for scaling luminance and chrominance are described in the fol- lowing sections. luminance scaling the ?st stage in horizontal luminance scaling is an optional pre-?ter which pro- vides the capability to reduce anti-aliasing artifacts. it is generally desirable to lim- it the bandwidth of the luminance spectrum prior to performing horizontal scaling because the scaling of high-frequency components may cause image artifacts in the resized image. the 3 mhz low pass ?ter shown in figure 9 reduces the hori- zontal high-frequency spectrum in the luminance signal. the bt819a implements horizontal scaling through poly-phase interpolation. the bt819a uses 32 different phases to accurately interpolate the value of a pixel. this provides an effective pixel jitter of 6 ns. in simple pixel- and line-dropping algorithms, non-integer scaling ratios intro- duce a step function in the video signal that effectively introduces high-frequency spectral components. poly-phase interpolation accurately interpolates to the cor- rect pixel and line position providing more accurate information. this results in aesthetically pleasing video as well as higher compression ratios in bandwidth lim- ited applications. for vertical scaling, the bt819a uses a 768x8-bit line store to im- plement a 2-tap, 8-phase interpolation ?ter. the bt817a and bt815a employ line dropping for vertical scaling. figure 12. filtering and scaling note: z ? refers to a pixel delay in the horizontal direction, and a line delay in the vertical direction. the coefficients are determined by ultralock and the scaling algorithm c hrominance 1 2 -- - 1 2 -- -z 1 + = l uminance cdz 1 + = v ertical s caler l uminance abz 1 cz 2 dz 3 ez 4 fz 5 +++++ = c hrominance ghz 1 + = h orizontal s caler 6 t ap , 32 p hase i nterpolation 768 x 8 l ine s tore 2 l ine , 8 p hase and h orizontal s caling 2 t ap , 32 p hase i nterpolation 768 x 8 l ine s tore and and h orizontal s caling c hroma c omb l ow p ass f ilter y y c c o ptional h orizontal v ertical s caling v ertical s caling (c hroma c omb ) 3 mh z
22 f unctional d escription video scaling, cropping, and temporal decimation bt819a/7a/5a chrominance scaling a 2-tap, 32-phase interpolation ?ter is used for horizontal scaling of chrominance. vertical scaling of chrominance is implemented through simple decimation or line dropping, followed by chrominance comb ?tering using a 768x8-bit line store. scaling registers the horizontal scaling ratio register (hscale) is programmed with the hor- izontal scaling ratio. when outputting unscaled video (in ntsc), the bt819a will output 910 pixels per line. this corresponds to the pixel rate at f clkx1 (4*fsc). this register is the control for scaling the video to the desired size. for example, square pixel ntsc requires 780 samples per line, while ccir601 requires 858 samples per line. hscale_hi and hscale_lo are two 8-bit registers that, when concatenated, form the 16-bit hscale register. the method below uses pixel ratios to determine the scaling ratio. as such, no ?ating point math is involved. this is an advantage in certain applications, such as when the scaling is being dynamically controlled by the user with a mouse. the following formula should be used to determine the scaling ratio to be entered into the 16-bit register: for example, to scale pal input to square pixel qcif, the total number of horizon- tal pixels is 236: an alternative method for determining the hscale value uses the ratio of the scaled active region to the unscaled active region as shown below: in this equation, the hactive value cannot be cropped; it represents the total ac- tive region of the video line. this equation produces roughly the same result as us- ing the full line length ratio shown in the ?st example. however, due to truncation, the hscale values determined using the active pixel ratio will be slightly differ- ent than those obtained using the total line length pixel ratio. the values in table 3 were calculated using the full line length ratio. ntsc: hscale = [ ( 910/p desired ) ?1] * 4096 pal: hscale = [ ( 1135/p desired ) ?1] * 4096 where: p desired = desired number of pixels per line of video, includ- ing active, sync and blanking. hscale = [ ( 1135/236 ) ?1 ] * 4096 = 15602 = 0x3cf2 ntsc: hscale = [ (754 / hactive) ?1] * 4096 pal: hscale = [ (922 / hactive) ?1] * 4096 where: hactive = desired number of pixels per line of video, not in- cluding sync or blanking.
23 f unctional d escription video scaling, cropping, and temporal decimation bt819a/7a/5a the vertical scaling ratio register (vscale) is programmed with the ver- tical scaling ratio. it de?es the number of vertical lines output by the bt819a. the following formula should be used to determine the value to be entered into this 13-bit register. the loaded value is a twos-complement, negative value. for example, to scale pal input to square pixel qcif, the total number of vertical lines is 156: note that only the 13 least signi?ant bits of the vscale value are used. the ?e lsbs of vscale_hi and the 8-bit vscale_lo register form the 13-bit vscale register. the three msbs of vscale_hi are used to control other functions. the user must take care not to alter the values of the three most signi?ant bits when writing a vertical scaling value. the following c-code fragment illustrates changing the vertical scaling value: #define byte unsigned char #define word unsigned int #define vscale_hi 0x13 #define vscale_lo 0x14 byte readfrombt819a( byte regaddress ); void writetobt819a( byte regaddress, byte regvalue ); void setbt819avscaling( word vscale ) { byte oldvscalemsbyte, newvscalemsbyte; /* get existing vscalemsbyte value from */ /* bt819a vscale_hi register */ oldvscalemsbyte = readfrombt819a( vscale_hi ); /* create a new vscalemsbyte, preserving top 3 bits */ newvscalemsbyte = (oldvscalemsbyte & 0xe0) | (vscale >> 8); /* send the new vscalemsbyte to the vscale_hi reg */ writetobt819a( vscale_hi, newvscalemsbyte ); /* send the new vscalelsbyte to the vscale_lo reg */ writetobt819a( vscale_lo, (byte) vscale ); } vscale = ( 0x10000 ?{ [ ( scaling_ratio ) ?1] * 512 } ) & 0x1fff vscale = ( 0x10000 ?{ [ ( 4/1 ) - 1 ] * 512 } ) & 0x1fff = 0x1a00 where: & = bitwise and | = bitwise or >> = bit shift, msb to lsb
24 f unctional d escription video scaling, cropping, and temporal decimation bt819a/7a/5a if your target machine has suf?ient memory to statically store the scaling val- ues locally, the read operation can be eliminated. note on vertical scaling: when scaling below cif resolution, it may be useful to use a single ?ld as opposed to using both ?lds. using a single ?ld will ensure there are no inter-?ld motion artifacts on the scaled output. when performing sin- gle ?ld scaling, the vertical scaling ratio will be twice as large as when scaling with both ?lds. for example, cif scaling from one ?ld does not require any ver- tical scaling, but when scaling from both ?lds, the scaling ratio is 50%. also, the non-interlaced bit should be reset when scaling from a single ?ld (int=0 in the vscale_hi register). table 3 lists scaling ratios for various video formats, and the register values required. image cropping cropping enables the user to output any subsection of the video image. the active ?g can be programmed to start and stop at any position on the video frame as shown in figure 13. the start of the active area in the vertical direction is referenced to vreset (beginning of a new ?ld). in the horizontal direction it is referenced to hreset (beginning of a new line). the dimensions of the active video region are de?ed by hdelay, hactive, vdelay, and vactive. all four registers are 10-bit values. the two msbs of each register are contained in the crop register, while the lower eight bits are in the respective hdelay_lo, hactive_lo, vdelay_lo and vactive_lo registers. the vertical and horizontal delay values determine the position of the cropped image within a frame while the horizontal and vertical active values set the pixel dimensions of the cropped image as illustrated in figure 13. table 3. scaling ratios for popular formats using frequency values scaling ratio format total resolution (including sync and blanking interval) output resolution (active pixels) hscale register values vscale register values use both fields single field full resolution 1:1 ntsc sq pixel ntsc ccir601 pal ccir601 pal sq pixel 780x525 858x525 864x625 944x625 640x480 720x480 720x576 768x576 0x02aa 0x00f8 0x0504 0x033c 0x0000 0x0000 0x0000 0x0000 n/a n/a n/a n/a cif 2:1 ntsc sq pixel ntsc ccir601 pal ccir601 pal sq pixel 390x262 429x262 432x312 472x312 320x240 360x240 360x288 384x288 0x1555 0x11f0 0x1a09 0x1679 0x1e00 0x1e00 0x1e00 0x1e00 0x0000 0x0000 0x0000 0x0000 qcif 4:1 ntsc sq pixel ntsc ccir601 pal ccir601 pal sq pixel 195x131 214x131 216x156 236x156 160x120 180x120 180x144 192x144 0x3aaa 0x3409 0x4412 0x3cf2 0x1a00 0x1a00 0x1a00 0x1a00 0x1e00 0x1e00 0x1e00 0x1e00 icon 8:1 ntsc sq pixel ntsc ccir601 pal ccir601 pal sq pixel 97x65 107x65 108x78 118x78 80x60 90x60 90x72 96x72 0x861a 0x7813 0x9825 0x89e5 0x1200 0x1200 0x1200 0x1200 0x1a00 0x1a00 0x1a00 0x1a00
25 f unctional d escription video scaling, cropping, and temporal decimation bt819a/7a/5a figure 13. effect of the cropping and active registers r ising edge of vreset f alling edge of hreset video frame hactive hdelay vdelay vactive video frame hactive hdelay vdelay vactive cropped image cropped image scaled to 1/2 size
26 f unctional d escription video scaling, cropping, and temporal decimation bt819a/7a/5a cropping registers the horizontal delay register (hdelay) is programmed with the delay be- tween the falling edge of hreset and the rising edge of active. the count is programmed with respect to the scaled frequency clock. note that hdelay should always be an even number. the horizontal active register (hactive) is programmed with the actual number of active pixels per line of video. this is equivalent to the number of scaled pixels that the bt819a should generate on a line. for example, if this register con- tained 90, and hscale was programmed to downscale by 4:1, then 90 active pix- els would be output. the 90 pixels would be a 4:1 scaled image of the 360 pixels (at clkx1) starting at count hdelay. hactive is restricted in the following manner: hactive + hdelay total number of scaled pixels. for example, in the ntsc square pixel format, there is a total of 780 pixels, in- cluding blanking, sync and active regions. therefore: hactive + hdelay 780. when scaled by 2:1 for cif, the total number of active pixels is 390. therefore: hactive +hdelay 390. the hdelay register is programmed with the number of scaled pixels be- tween hreset and the ?st active pixel. because the front porch is de?ed as the distance between the last active pixel and the next horizontal sync, the video line can be considered in three components: hdelay, hactive and the front porch. see figure 14. when cropping is not implemented, the number of clocks at the 4x sample rate (the clkx1 rate) in each of these regions is shown below: the value for hdelay is calculated using the following formula: hdelay = [(clkx1_hdelay / clkx1_hactive) * hactive] & 0x3fe clkx1_hdelay and clkx1_hactive are constant values, so the equation becomes: ntsc: hdelay = [(135 / 754) * hactive] & 0x3fe pal: hdelay = [(186 / 922) * hactive] & 0x3fe clkx1 front porch clkx1 hdelay clkx1 hactive clkx1 total ntsc 21 135 754 910 pal 27 186 922 1135
27 f unctional d escription video scaling, cropping, and temporal decimation bt819a/7a/5a the vertical delay register (vdelay) is programmed with the delay be- tween the rising edge of vreset and the start of active video lines. it determines how many lines to skip before initiating the active signal. it is programmed with the number of lines to skip at the beginning of a frame. the vertical active register (vactive) is programmed with the number of lines used in the vertical scaling process. the actual number of vertical lines output from the bt819a is equal to this register times the vertical scaling ratio. if vscale is set to 0x1a00 (4:1) then the actual number of lines output is vactive/4. if vscale is set to 0x0000 (1:1) then vactive contains the actual number of vertical lines output. note: it is important to note the difference between the implementation of the horizontal registers (hscale, hdelay, and hactive) and the vertical registers (vscale, vdelay, and vactive). horizontally, hdelay and hactive are programmed with respect to the scaled pixels de?ed by hscale. vertically, vdelay and vactive are programmed with respect to the number of lines before scaling (before vscale is applied). temporal decimation temporal decimation provides a solution for video synchronization during periods when full frame rate can not be supported due to bandwidth and system restric- tions. for example, when capturing live video for storage, system limitations such as hard disk transfer rates or system bus bandwidth may limit the frame capture rate. if these restrictions limit the frame rate to 15 frames per second, the bt819as time scaling operation will enable the system to capture every other frame instead of al- lowing the hard disk timing restrictions to dictate which frame to capture. this maintains an even distribution of captured frames and alleviates the ?erky?effects caused by systems that simply burst in data when the bandwidth becomes avail- able. the bt819a provides temporal decimation on either a ?ld or frame basis. the temporal decimation register (tdec) is loaded with a value from 1 to 60 (ntsc) or 1 to 50 (pal). this value is the number of ?lds or frames skipped by the chip during a sequence of 60 for ntsc or 50 for pal. skipped ?lds and frames are considered inactive, which is indicated by the active pin remaining low and qclk becoming inactive. figure 14. regions of the video signal hdelay hactive f ront p orch
28 f unctional d escription video scaling, cropping, and temporal decimation bt819a/7a/5a examples: when changing the programming in the temporal decimation register, 0x00 should be loaded ?st, and then the decimation value. this will ensure that the decimation counter is reset to zero. if zero is not ?st loaded, the decimation may start on any ?ld or frame in the sequence of 60 (or 50 for pal). on power-up, this preload is not necessary because the counter is internally reset. when decimating ?lds, the bt819a/7a/5a does not guarantee starting on an even or odd ?ld. tdec = 0x02 decimation is performed by frames. two frames are skipped per 60 frames of video, assuming ntsc decoding. frames 1?9 are output normally, then active remains low for one frame. frames 30?9 are then output followed by another frame of inactive video. tdec = 0x9e decimation is performed by fields. thirty fields are output per 60 fields of video, assuming ntsc decoding. this value outputs every other ?ld (every odd ?ld) of video starting with ?ld one in frame one. tdec = 0x01 decimation is performed by frames. one frame is skipped per 50 frames of video, assuming pal decoding. tdec = 0x00 decimation is not performed. full frame rate video is output by the bt819a.
29 f unctional d escription video adjustments bt819a/7a/5a video adjustments the bt819a provides programmable hue, contrast, saturation, and brightness. the hue adjust register (hue) the hue adjust register is used to offset the hue of the decoded signal. in ntsc, the hue of the video signal is de?ed as the phase of the subcarrier with reference to the burst. the value programmed in this register is added or subtracted from the phase of the subcarrier, which effectively changes the hue of the video. the hue can be shifted by plus or minus 90 degrees. because of the nature of pal encoding, hue adjustments can not be made when decoding pal. the contrast adjust register (contrast) the contrast adjust register (also called the luma gain) provides the ability to change the contrast from approximately 0% to 200% of the original value. the de- coded luma value is multiplied by the 9-bit coef?ient loaded into this register. the saturation adjust registers (sat_u, sat_v) the saturation adjust registers are additional color adjustment registers. it is a multiplicative gain of the u and v signals. the value programmed in these regis- ters are the coef?ients for the multiplication. the saturation range is from approx- imately 0% to 200% of the original value. the brightness register (bright) the brightness register is simply an offset for the decoded luma value. the pro- grammed value is added or subtracted from the original luma value which changes the brightness of the video output. the luma output is in the range of 0 to 255. brightness adjustment can be made over a range of ?4 to +63.
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31 e lectrical i nterfaces input interface analog signal selection the bt819a contains an on-chip 3:1 mux. this mux can be used to switch between three composite sources or two composite sources and one s-video source. in the ?st con?uration, connect the inputs of the mux (mux0, mux1 and mux2) to the three composite sources. in the second con?uration, connect two inputs to the composite sources and the other input to the luma component of the s-video con- nector. in both con?urations the output of the mux (muxout) should be con- nected to the input to the luma a/d (yin) and the input to the sync detection circuitry (syncdet). when implementing s-video, the input to the chroma a/d (cin) should be connected to the chroma signal of the s-video connector. use of the multiplexer is not a requirement for operation. if digitization of only one video source is required, the source may be connected directly to yin and syncdet. multiplexer considerations the multiplexer is not a break-before-make design. therefore, during the multi- plexer switching time it is possible for the input video signals to be momentarily connected together through the equivalent of 200 ohms. the multiplexers cannot be switched on a real-time pixel-by-pixel basis. autodetection of ntsc or pal video if the bt819a is con?ured to decode both ntsc and pal, the bt819a can be programmed to automatically detect which format is being input to the chip. au- todetection will select the proper clock source for the format detected, (if ntsc is detected then xtal0 is selected, if pal is detected xtal1 is selected.) alterna- tively, the decoding con?uration can be programmed by writing to the input for- mat register (0x01). the bt819a determines the video source input to the chip by counting the num- ber of lines in a frame. the result of this is indicated in bit numl in the status register. based on this bit, the format of the video is determined, and xt0 or xt1 is selected for the clock source. automatic format detection will select the clock source, but it will not program the required registers. the scaling and cropping reg- isters (vscale, hscale, vdelay, hdelay, vactive, and hactive) as well as the burst delay and agc delay registers (bdelay and adelay) must be programmed accordingly.
32 e lectrical i nterfaces input interface bt819a/7a/5a flash a/d converters the bt819a and bt817a use two on-chip ?sh a/d converters to digitize the video signals. yref+, cref+ and yref? cref?are the respective top and bottom of the internal resistor ladder. the input video is always ac-coupled to the decoder. cref?and yref?are connected to analog ground. the voltage levels for yref+ and cref+ are con- trolled by the gain control circuitry. if the input video momentarily exceeds the corresponding ref+ voltage it is indicated by lof and cof in the status reg- ister. the bt815a has only the luma a/d for decoding composite video. the chro- ma a/d pins are not available on the bt815a. a/d clamping an internally generated clamp control signal is used to clamp the inputs of the a/d converter for dc restoration of the video signals. clamping for both the yin and cin analog inputs occurs within the horizontal sync tip. the yin input is always restored to ground while the cin input is always restored to clevel. clevel must be set with an external resistor network so that it is biased to the midpoint be- tween cref?and cref+. external clamping is not required because internal clamping is automatically performed. automatic gain controls the refout, cref+ and yref+ pins should be connected together as shown in figure 15. in this con?uration, the bt819a controls the voltage for the top of the reference ladder for each a/d. the automatic gain control adjusts the yref+ and cref+ voltage levels until the back porch of the y video input generates a digital code 0x38 from the a/d. if the video being digitized has a non-standard sync height to video height ratio, the digital code used for agc may be changed by pro- gramming the adc interface register (0x1a). crystal inputs and clock generation the bt819a has two pairs of pins, xt0i/xt0o and xt1i/xt1o, that are used to input a clock source. if both ntsc and pal video are being digitized, both clock inputs must be implemented. the xt0 port is used to decode ntsc video and must be con?ured with a 28.63636 mhz source. the xt1 port is used to decode pal video and must be con?ured with a 35.46895 mhz source. if the bt819a is con?ured to decode either ntsc or pal but not both, then only one clock source must be provided to the chip and it must be connected to the xt0i/xt0o port. crystals are speci?d as follows: 28.636363 mhz or 35.468950 mhz third overtone parallel resonant 30 pf load capacitance 50 ppm series resistance 40 w or less
33 e lectrical i nterfaces input interface bt819a/7a/5a the following crystals are recommended for use with the bt819a: 1 standard : this vendor will support very short lead times. (818) 443-2121 2bak28m636363gle30a 2bak35m468950gle30a 2 mmd (714) 444-1402 a30aa3-28.63636mhz a30aa3-35.46895mhz 3 ged (619) 591-4170 pkhc49-28.63636-.030-005-40r, 3rd overtone crystal pkhc49-35.46895-.030-005-40r, 3rd overtone crystal 4 m-tron (800) 762-8800 mp-1 28.63636, 3rd overtone crystal mp-1 35.46895, 3rd overtone crystal 5 monitor (619) 433-4510 mm49x3c3a-28.63636, 3rd overtone crystal mm49x3c3a-35.46895, 3rd overtone crystal 6 cts (815) 786-8411 r3b55a30-28.63636, 3rd overtone crystal r3b55a30-35.46895, 3rd overtone crystal 7 fox (813) 693-0099 hc49u-28.63636, 3rd overtone crystal hc49u-35.46895, 3rd overtone crystal the two clock sources may be con?ured with either single-ended oscillators, fundamental cut crystals or third overtone mode crystals, parallel resonant. if sin- gle-ended oscillators are used they must be connected to xt0i and xt1i. the clock source options and circuit requirements are shown in figure 16. the clock source tolerance should be 50 parts-per-million (ppm) or less. devices that output cmos voltage levels are required. the load capacitance in the crystal con?urations may vary depending on the magnitude of board parasitic ca- pacitance. the bt819a is dynamic, and, to ensure proper operation, the clocks must be always running, with a minimum frequency of 28.64 mhz. the clkx1 and clkx2 outputs from the bt819a are generated from xt0 and xt1 clock sources. clkx2 operates at the crystal frequency (8xfsc) while clkx1 operates at half the crystal frequency (4xfsc).
34 e lectrical i nterfaces input interface bt819a/7a/5a figure 15. typical external circuitry 75 w 330 pf 330 pf 0.1 m f 3.3 m h 75 w 330 pf 330 pf 0.1 m f 3.3 m h 75 w 330 pf 330 pf 0.1 m f 3.3 m h mux1 mux2 cin * 0.1 m f 1 m w muxout yin syncdet cref?* yref clevel * refout yref+ cref+ * vaa 2 k w 0.1 m f 30 k w 30 k w 0.1 m f xt0i xt0o 2.7 m h 22 pf 33 pf 0.1 m f 28.63636 xt1i xt1o 2.2 m h 22 pf 33 pf 0.1 m f 35.46895 0.1 m f jtag i 2 c video timing anti-aliasing filter 75 w termination ac coupling capacitor 1 m w 1 m w mhz mhz analog ground digital ground * chroma a/d not available on bt815a 0.1 m f vaa vpos agccap vneg 75 w 330 pf 330 pf 0.1 m f 3.3 m h mux0
35 e lectrical i nterfaces input interface bt819a/7a/5a figure 16. clock options pal third overtone mode crystal oscillator 2.2 m h 33 pf 0.1 m f 22 pf xt1i xt1o 35.46895 mhz ntsc third overtone mode crystal oscillator 2.7 m h 33 pf 0.1 m f 22 pf xt0i xt0o 28.63636 mhz xt1i xt1o xt0i xt0o 47 pf 47 pf 28.63636 mhz 47 pf 47 pf 35.46895 mhz pal fundamental crystal oscillator ntsc fundamental crystal oscillator 1 m w 1 m w 1 m w 1 m w xt1i xt1o xt0i xt0o pal single-ended oscillator ntsc single-ended oscillator osc osc 28.63636 mhz 35.46895 mhz
36 e lectrical i nterfaces input interface bt819a/7a/5a 2x oversampling and input filtering digitized video needs to be bandlimited in order to avoid aliasing artifacts. be- cause the bt819a samples at clkx2 (8xfsc - twice the normal rate) the analog ?- tering required at the input to the a/ds is minimal. the analog video needs to be band limited to 14 mhz. the suggested ?ters to do this are shown in figure 15. after digitization, the samples are digitally low pass ?tered and then decimated to clkx1. the response of this low pass ?ter is shown in figure 17. the digital low pass ?ter provides additional bandwidth reduction to limit the video to 6 mhz. figure 17. luma & chroma 2x oversampling filter ntsc pa l ntsc pa l
37 e lectrical i nterfaces output interface bt819a/7a/5a output interface output interfaces the bt819a supports two output interfaces: the synchronous pixel interface (spi) and the asynchronous pixel interface (api). the spi can support 8-bit or 16-bit ycrcb 4:2:2 data streams, api supports a 16-bit data stream. in the spi mode, bt819a outputs all pixel and control data synchronous with clkx1 (16-bit mode), or clkx2 (8-bit mode). events such as hreset and vreset may also be encoded as control codes in the data stream to enable a re- duced pin interface (bytestream ? ). in the api mode, only the active pixel data is output synchronous with the clkin provided by the system. the pixels are output via a 40-pixel-deep, 16-bit-wide fifo. hreset and vreset are always output on independent pins and, when programmed, are coded onto the data stream. mode selections are controlled by the state of the oform register. figure 18 shows a diagram summarizing the different operating modes. each mode will be covered in detail individually. on power-up, the bt819a automatically initializes to spi mode 1, 16 bits wide. ycrcb pixel stream format, spi mode 8- and 16-bit formats when the output is con?ured for an 8-bit pixel interface, the data is output on pins vd[15:8] with the 8 bits of chrominance data preceding 8 bits of luminance data for each pixel. new pixel data is output on the pixel port after each rising edge of clkx2. when the output is con?ured for the 16-bit pixel interface, the luminance data is output on vd[15:8], and the chrominance data is output on vd[7:0]. in 16-bit mode, the data is output with respect to clkx1. see table 4 for a summary of output interface con?urations. the ycrcb 4:2:2 pixel stream follows the ccir recommendation as illustrated in figure 19. figure 18. output mode summary (api mode only for bt819a) spi api 8-bit 16-bit 8-bit 16-bit parallel control (spi mode 1) coded control (spi mode 2) (bytestream ? ) pixel burst, 819a controlled pixel burst, system controlled (api mode a, bt819a only) (api mode b, bt819a only)
38 e lectrical i nterfaces output interface bt819a/7a/5a synchronous pixel interface (spi, mode 1) upon reset, the bt819a initializes to the spi output mode 1. in this mode, bt819a outputs all horizontal and vertical blanking interval pixels in addition to the active pixels synchronous with clkx1 (16-bit mode), or clkx2 (8-bit mode). in the spi-1 mode, the bt819a output interface is similar to the bt812 output interface. figure 20 illustrates bt819a spi-1. figure 21 illustrates the basic timing relation- ships in the spi modes. the relationships remain the same for the 16-bit or 8-bit modes. the 16-bit modes use clkx1 as the reference, and the 8-bit modes use clkx2. figure 23 shows the video timing for spi modes 1 and 2. table 4. pixel/pin map 16-bit pixel interface pin name vd15 vd14 vd13 vd12 vd11 vd10 vd9 vd8 vd7 vd6 vd5 vd4 vd3 vd2 vd1 vd0 data bit y7 y6 y5 y4 y3 y2 y1 y0 crcb7 crcb6 crcb5 crcb4 crcb3 crcb2 crcb1 crcb0 8-bit pixel interface pin name vd15 vd14 vd13 vd12 vd11 vd10 vd9 vd8 vd7 vd6 vd5 vd4 vd3 vd2 vd1 vd0 y data bit y7 y6 y5 y4 y3 y2 y1 y0 c data bit crcb7 crcb6 crcb5 crcb4 crcb3 crcb2 crcb1 crcb0 figure 19. ycrcb 4:2:2 pixel stream format (spi mode, 8 and16 bits) 8-b it p ixel i nterface clk x 1 16-b it p ixel i nterface c b 0 y0 c r 0 y1 c b 2 y2 c r 2 y3 c b 0 c r 0 y0 y1 c b 2 c r 2 y2 y3 vd[15:8] vd[15:8] vd[7:0] clk x 2
39 e lectrical i nterfaces output interface bt819a/7a/5a figure 20. bt819a, bt817a, bt815a synchronous pixel interface, mode 1 (spi-1) hreset vreset active dvalid cbflag field vd[15:0] oe 16 clk x 1 (4*f sc ) bt819a clk x 2 (8*f sc ) qclk figure 21. basic timing relationships for spi mode 1. vd[15:0] dvalid active clk x 1 or clk x 2 qclk c b flag
40 e lectrical i nterfaces output interface bt819a/7a/5a synchronous pixel interface (spi, mode 2, bytestream) in spi mode 2, the bt819a encodes all video timing control signals onto the pixel data bus. bytestream ? is the 8-bit version of this con?uration. because all tim- ing data is included on the data bus, a complete interface to a video controller can be implemented in only 9 pins: one for clkx2 and eight for data. when using coded control, the range bit and the code bit must be pro- grammed high. when the range bit is high, the chrominance pixels (both cr and cb) are saturated to the range 2 to 253, and the luminance range is limited to the range 16 to 253. in spi mode 2, the chroma values of 255 and 254, and the lumi- nance values of 0 to 15 are inserted as control codes to indicate video events (table 5). chroma value of 255 is used to indicate that the associated luma pixel is a control code; pixel value of 255 also indicates that the cbflag is high (i.e. the current pixel is a cb pixel). similarly, a pixel value of 254 indicates that the luma value is a control code, and the cbflag is low (cr pixel). the ?st pixel of a line is guaranteed to be a cb ?g;however, due to code pre- cedence relationships, the hreset code may be delayed by one pixel, so hreset can occur on a cr or a cb pixel. also, at the beginning of a new ?ld the relationship between vreset and hreset may be lost, typically with video from a vcr. as a result, vreset can occur during either a cb or a cr pixel. figure 22 demonstrates coded control for spi mode 2 (bytestream). pixel data output ranges are shown in table 6. independent of range, decimal 128 indicates zero color information for cr and cb. black is decimal 16 when range=0, and code 0 when range=1. table 7 provides a summary of the control sifnal functions for the spi modes. table 5. description of the control codes in the pixel stream luma value chroma value video event description 0x00 0xff 0xfe this is an invalid pixel; last valid pixel was a cb pixel this is an invalid pixel; last valid pixel was a cr pixel 0x01 0xff 0xfe cb pixel; last pixel was the last active pixel of the line cr pixel; last pixel was the last active pixel of the line 0x02 0xff 0xfe cb pixel; next pixel is the ?st active pixel of the line cr pixel; next pixel is the ?st active pixel of the line 0x03 0xff 0xfe cb pixel; hreset of a vertical active line cr pixel; hreset of a vertical active line 0x04 0xff 0xfe cb pixel; hreset of a vertical blank line cr pixel; hreset of a vertical blank line 0x05 0xff 0xfe cb pixel; vreset followed by an even ?ld cr pixel; vreset followed by an even ?ld 0x06 0xff 0xfe cb pixel; vreset followed by an odd ?ld cr pixel; vreset followed by an odd ?ld
41 e lectrical i nterfaces output interface bt819a/7a/5a ccir 601 compliance when the range bit is set to zero, the output levels are fully compliant with the ccir 601 recommendation. ccir 601 speci?s that nominal video will have y values ranging from 16 to 235, and cr and cb values ranging from 16 to 240. how- ever, excursions outside this range are allowed to handle non-standard video. the only mandatory requirement is that 0 and 255 be reserved for timing information. table 6. data output ranges range = 0 range = 1 y 16 ? 253 0 ? 255 cr 2 ? 253 2 ? 253 cb 2 ? 253 2 ? 253 figure 22. data output in spi mode 2 (bytestream) clk x 2 vd(15:0) 0 x ff 0 x 04 0 x ff 0 x 03 ?? hreset , beginning of horizontal line during active video c b pixel c b pixel hreset , beginning of horizontal line during vertical blanking ?? ?? ?? ?? ?? ?? ?? ?? ?? 0 x ff 0 x 02 c b yc r y f irst active pixel of the line i nvalid pixel during active video l ast valid pixel was a c b pixel c b y0 x ff 0 x 00 c r y c b y0 x fe 0 x 01 xx xx l ast pixel of the line (c b pixel ) l ast pixel code (c r pixel ) c r pixel vreset ; an odd field follows xx xx 0 x fe 0 x 06 xx xx active pixel of the line n ext pixel is first
42 e lectrical i nterfaces output interface bt819a/7a/5a table 7. synchronous pixel interface (spi) control signals signal description hreset a 64-clock-long active low pulse. it is output following the rising edge of clkx1. the falling edge of hreset indicates the begin- ning of a new video line. see figure 23 and figure 24. vreset an active low signal that is at least two lines long (for non-vcr sources, vreset is normally six lines long). it is output following the rising edge of clkx1. the falling edge of vreset indicates the beginning of a new ?ld of video output. the falling edge of vreset lags the falling edge of hreset by two clock cycles at the start of an odd ?ld. at the start of even ?lds, the falling edge of vreset is in the middle of a scan line, horizontal count (hpixel/2)+1, on scan line 263 for ntsc and scan line 313 for pal (figure 23). active an active high signal that indicates the beginning of the active video and is output following the rising edge of clkx1. the active ?g is used to indicate where nonblanking pixels are present. the start and the end of the active signal can be adjusted by programming the vdelay, vactive, hdelay, and hactive registers via the i 2 c interface. see figure 23 and figure 24. dvalid an active high pixel quali?r that indicates whether or not the associated pixel is valid. dvalid is independent of the active signal. the active signal is programmed to output a certain set of pixels. dvalid indicates which pixels are valid within this win- dow. dvalid will toggle high outside of the active window, indi- cating a valid pixel outside the programmed active region. cbflag an active high pulse that indicates when cb data is being output on the chroma stream. during invalid pixels, cbflag holds the value of the last valid pixel. field when high, indicates that an even ?ld (?ld 2) is being output; when low it indicates that an odd ?ld (?ld 1) is being output. the transition of field is synchronous with the end of active video (i.e. the trailing edge of active). the same information can also be derived by latching the hreset signal with vreset (figure 23). vd[15:0] the digital output pins for the video data stream. clkx1 the 4*fsc clock output for the format (ntsc or pal) currently selected. the data is output based on this clock in spi, 16-bit mode. clkx2 the 8*fsc clock output for the format (ntsc or pal) currently selected. the data is output based on this clock in spi, 8-bit mode. qclk a quali?d clock output. this pin provides a rising edge only dur- ing valid, active pixel data. this output is generated from clkx1 (or clkx2 in 8-bit mode), active and dvalid. the phase of qclk is inverted from the clkx1 (or clkx2) to ensure adequate setup and hold time with respect to the data outputs. qclk is not output during control codes when using spi mode 2.
43 e lectrical i nterfaces output interface bt819a/7a/5a figure 23. video timing in spi modes 1 and 2 notes: (1). hreset precedes vreset by two clock cycles at the beginning of fields 1, 3, 5 and 7 to facilitate external field generation. 2. active, hreset, vreset and field are shown here with their default polarity. the polarity is program- mable via the vpole register. 3. field transitions with the end of horizontal active video de?ed by hdelay and hactive. 2? scan lines hreset vreset active field vdelay/2 scan lines b eginning of fields 1, 3, 5, 7 (1) 2? scan lines hreset vreset active field vdelay/2 scan lines b eginning of fields 2, 4, 6, 8
44 e lectrical i nterfaces output interface bt819a/7a/5a figure 24. horizontal timing signals in the spi modes hdelay c lock c ycles at f d esired hactive c lock c ycles at f d esired 64 c lock c ycles at f clk x 1 hreset active
45 e lectrical i nterfaces output interface bt819a/7a/5a asynchronous pixel interface (api) (bt819a only) in the api modes, the pixel stream generated by the bt819a is buffered prior to the pixel port outputs by a 40-pixel-deep fifo. the fifo input sees a pixel stream coming in 4*fsc pixels/s. the number of acquired samples or pixels is reduced at the fifo input by using a pixel quali?r of valid ?g that indicates which pixels are to be dropped (i.e., not written into the fifo). thus, the bt819a only writes ac- tive, valid video pixels and control codes into the fifo. when the output is oper- ating asynchronously, clkin is used to clock pixels out of the fifo. clkin must be fast enough that the fifo does not over?w. thus, clkin must operate faster than the effective write rate to the fifo. figure 25 illustrates the basic interface. this rate is determined by the number of active pixels per line. for example, in square pixel ntsc, there are 640 active pixels per line input to the fifo over a pe- riod of about 52 m s. as long as the clkin rate is greater than 12.27 mhz, the fifo will never over?w. api can be used with the external video timing signals, or with coded control signals on the video data bus (as in spi mode 2). however, in api mode, only the last active pixel and vreset codes are output (luma values 0x01, 0x05 and 0x06.) in api mode, the control codes are output during either the blanking interval or during invalid data. mode a: fifo controlled by bt819a (bt819a only) in api mode a, the bt819a controls the fifo. dvalid is fed back to rden in- ternally. this mode is programmed via the fifo_burst bit in the oform reg- ister. unlike in spi mode, dvalid makes no statement about the validity of the current pixel in api. dvalid acts as an indication of how much data is stored in the fifo. dvalid will go high at the same time that the almost full flag (aff) goes high, and will go low when the fifo is empty. rden is an input control which allows data to be read from the fifo. by internally connecting dvalid to rden, the user can be assured that the fifo never over?ws. figure 25. asynchronous pixel interface (api) 16 hreset cbflag dvalid aef vd[15:0] oe clk x 1 (4*f sc ) clk x 2 (8*f sc ) bt819a vreset field clkin rden aff qclk frst
46 e lectrical i nterfaces output interface bt819a/7a/5a in mode a clkin must be connected to clkx1 . data will be present at the vd outputs whenever valid data are in the fifo. there are two indicators of the status of the data present at the fifo output. one is the dvalid pin. although this signal is connected internally to the rden pin, the signal is still present at the dvalid pin itself. dvalid will go high one clkin cycle before valid data is present. the second indicator of valid data is the qclk signal. this pin provides a quali?d clock output, based upon clkin, and gated by the presence of readable data in the fifo. qclk may be used as a load clock for capturing data from the fifo. these timing relationships are shown in figure 26 and figure 27. while dvalid indicates there is data in the fifo, active or qclk must be used to differentiate between pixel information and control codes. dvalid indicates the presence of both while active and qclk indicate the presence of only active valid pixels. after the last pixel is read from the fifo, the data bus and control signals are unde?ed. mode b: fifo controlled by system (bt819a only) api mode b is similar to mode a. the only difference is that the dvalid signal is not connected internally to rden. the user must monitor the almost full flag (aff), and the almost empty flag (aef), and control rden manually. in api mode b, qclk is continuous, and not gated (effectively a delayed output of clkin). the timing relationships for api mode b are shown in figure 28. in ad- dition, figure 28 shows an external circuit that can be used to control rden using the aef and aff ?gs. note: in api mode b, the fifo should not be emptied while active video data is being written into the fifo. if the fifo is emptied during the active video line, the last two or three pixels read out of the fifo will be corrupted. to avoid this, simply use the aef and aff ?gs to control rden as shown in figure 28.
47 e lectrical i nterfaces output interface bt819a/7a/5a figure 26. basic timing relationships for api mode a vd[15:0] dvalid clkin qclk aff aef fifo becomes almost full (aff=1), then is unloaded until the fifo is empty fifo is nearing empty fifo is now empty (rden) (clk x 1) figure 27. api-a datastream during a field transition clkin qclk dvalid vd[15:0] hreset vreset aff l ast pixel in last line of f ield z f irst pixel in the first line of f ield z+1 0 x 1ff 0 x 5fe c b flag (rden) (clk x 1)
48 e lectrical i nterfaces output interface bt819a/7a/5a asynchronous pixel interface control signals figure 26, figure 27 and table 8 demonstrate the operation of the video timing signals in api mode. as shown in these diagrams, the control codes for hreset and vreset are also included in the pixel data stream. this enables a smaller pin count interface to the bt819a should that be a system requirement. the full video timing interface is also available, and de?ed in table 9. figure 28. basic timing relationships for api mode b clkin rden aff aef vd[0:15] qclk l ast pixel 32 or 20 pixels in fifo aef aff rden p ossible circuit for external generation of rden read
49 e lectrical i nterfaces output interface bt819a/7a/5a table 8. operation of timing signals, api (both modes a and b) rden active hreset vreset vd[15:0] comment line transition 11 1 1 a (1) 11 1 1 a 11 1 1 a 1 1 1 1 a last pixel of old line. 10 0 1 h (2) end of video line (code 01ff or 01fe). 1 1 1 1 a first pixel of new line. 01 1 1 a 0 0 x x x stop reading from fifo. 00xxx 00xxx . . . . . . . . . . field transition 00xxx 10xxx 11 1 1 a 1 1 1 1 a last pixel in last line of ?ld z. 10 0 1 h (2) end of video line (code 01ff or 01fe). 10 1 0 v (2) field transition (code 05ff for example). 1 1 1 1 a first pixel in ?st line of ?ld z+1. 11 1 1 a . . . . . . . . . . field transition (fifo read until empty) 00xxx 10xxx 11 1 1 a 11 1 1 a 10 0 1 h (2) 00 1 0 v (2) field transition (code 06ff for example). 00xxx 00xxx 00xxx notes: (1). ??indicates active pixel data. (2). if the code bit is programmed low (disabling code outputs) the data on the vd bus is invalid. all other outputs remain the same.
50 e lectrical i nterfaces output interface bt819a/7a/5a table 9. asynchronous pixel interface control signals, bt819a only (1 of 2) pin name comments hreset a one-clock-cycle-wide active low pulse. it is output after the last active pixel of a line, and it indicates that the next pixel is the ?st pixel of the next active line. when the fifo happens to empty at the end of a line, hreset remains low until another valid pixel, or vreset . vreset a one-clock-cycle-wide active low pulse. it is output after hreset for the last line in the ?ld. the next pixel is the ?st active pixel of the next ?ld. field when high, indicates an even ?ld (?ld 2); when low it indicates an odd ?ld (?ld 1). field information does not get buffered through the fifo. cbflag a one-clock-cycle-wide active high pulse that indicates that cb chroma data is being output. dvalid goes high when the fifo has 20 locations ?led. this pin will remain high until the fifo is empty. when the fifo output rate is the same as the clkin rate, dvalid can be connected to rden to provide a continuous pixel data stream. dvalid may also be used to gate dma cycles from the fifo. dvalid may be programmed to toggle high when the fifo holds 32 pixels. aff an active high pulse. it transitions high when there are more than 31 pixels of valid data in the fifo and stays high as long as 32 or more pixels are in the fifo to be read. this ?g may be programmed to toggle high when the fifo holds 20 pixels. this is useful in api mode b. aef almost empty flag. indicates that the fifo is about to empty. note: the aef ?g is pipelined to the output of the chip. also, the fifo is being written into during this time. therefore, the actual num- ber of pixels in the fifo when aef toggles will vary. the number of pixels remaining could be as low as 2 or as high as 8. the system should stop reading from the fifo as soon as aef indicates almost empty. see figure 28 for a recommended circuit.
51 e lectrical i nterfaces output interface bt819a/7a/5a vd[15:0] the digital output pins for the video data stream. rden a read enable for the fifo. when rden is high and there is data in the fifo, a positive edge on clkin outputs a pixel on vd[15:0]. clkin the clock that determines the transfer rate of data from the bt819a in the api mode. when rden is high, this clock puts pixel data on vd[15:0]. clkx1 the 4*fsc clock output for the format (ntsc or pal) currently selected. clkx2 the 8*fsc clock output for the format (ntsc or pal) currently selected. qclk in mode a, qclk will generate a clock edge only during active, valid pixels, not during control codes. may be used as a load clock signal with the pixel data. in mode b, qclk is continuous and not gated (effectively a delayed output of clkin). active indicates valid pixel data out of the fifo. this pin toggles high at the same time as dvalid except that dvalid is also high during control codes. frst fifo reset. driving this pin low for at least 4 clkin cycles will reset the fifo. table 9. asynchronous pixel interface control signals, bt819a only (2 of 2) pin name comments
52 e lectrical i nterfaces i 2 c interface bt819a/7a/5a i 2 c interface the inter-integrated circuit (i 2 c) bus is a two-wire serial interface. serial clock and data lines, scl and sda, are used to transfer data between the bus master and the slave device. the bt819a can transfer data at a maximum rate of 100 kbits/s. the bt819a operates as a slave device. starting and stopping the relationship between scl and sda is decoded to provide both a start and stop condition on the bus. to initiate a transfer on the i 2 c bus, the master must transmit a start pulse to the slave device. this is accomplished by taking the sda line low while the scl line is held high. the master should only generate a start pulse at the beginning of the cycle, or after the transfer of a data byte to or from the slave. to terminate a transfer, the master must take the sda line high while the scl line is held high. the master may issue a stop pulse at any time during an i 2 c cycle. since the i 2 c bus will interpret any transition on the sda line during the high phase of the scl line as a start or stop pulse, care must be taken to ensure that data is stable during the high phase of the clock. this is illustrated in figure 29. addressing the bt819a an i 2 c slave address consists of two parts: a 7-bit base address and a single bit r/w command. the r/w bit is appended to the base address to form the transmit- ted i 2 c address, as shown in figure 30 and table 10. figure 29. the relationship between scl and sda s tart s top sda scl figure 30. i 2 c slave address con?uration a6 a5 a4 a3 a2 a1 a0 r/w b ase a ddress r/w b it
53 e lectrical i nterfaces i 2 c interface bt819a/7a/5a reading and writing after transmitting a start pulse to initiate a cycle, the master must address the bt819a. to do this, the master must transmit one of the four valid bt819a address- es, most signi?ant bit (msb) ?st. after transmitting the address, the master must release the sda line during the low phase of the serial clock, scl, and wait for an acknowledge. if the transmitted address matches the selected bt819a ad- dress, the bt819a will respond by driving the sda line low, generating an ac- knowledge to the master. the master will sample the sda line at the rising edge of the scl line, and proceed with the cycle. if no device responds, including the bt819a, the master transmits a stop pulse and ends the cycle. if the slave address r/w bit was low, indicating a write, the master will transmit an 8-bit byte to the bt819a, msb ?st. the bt819a will acknowledge the transfer and load the data into its internal address register. the master may now issue a stop command, a start command, or transfer another 8-bit byte, msb ?st, to be loaded into the register pointed to by the internal address register. the bt819a will then acknowledge the transfer and increment the address register in preparation for the next transfer. as before, the master may now issue a stop command, a start com- mand, or transfer another 8 bits to be loaded into the next location. if the slave address r/w bit was high, indicating a read, the bt819a will trans- fer the contents of the register pointed to by its internal address register, msb ?st. the master should acknowledge the receipt of the data and pull the sda line low. as with the write cycle, the address register will be autoincremented in preparation for the next read. to stop a read transfer, the host must not acknowledge the last read cycle. the bt819a will then release the data bus in preparation for a stop command. if an ac- knowledge is received, the bt819a will proceed to transfer the next register. when the master generates a read from the bt819a, the bt819a will start its transfer from whatever location is currently loaded in the address register. since the address register may not contain the address of the desired register, the master should execute a write cycle, setting the address register to the desired location. after receiving an acknowledge for the transfer of the data into the address regis- ter, the master should initiate a read of the bt819a by starting a new i 2 c cycle with an appropriate read address. the bt819a will now transfer the contents of the de- sired register. for example, to read register 0x0a, brightness control, the master should start a write cycle with an i 2 c address of 0x88 or 0x8a. after receiving an acknowledge from the bt819a, the master should transmit the desired address, 0x0a. after re- table 10. bt819a address matrix i2ccs pin bt819a base r/w bit action 0 1000100 0 write 1000100 1 read 1 1000101 0 write 1000101 1 read
54 e lectrical i nterfaces i 2 c interface bt819a/7a/5a ceiving an acknowledge, the master should then start a read cycle with an i 2 c slave address of 0x89 or 0x8b. the bt819a will then acknowledge and transfer the con- tents of register 0x0a. it should be noted that there is no need to issue a stop com- mand after the write cycle. the bt819a will detect the repeated start command, and start a new i 2 c cycle. this process is illustrated in table 11 and figure 31. for detailed information on the i 2 c bus, refer to ?he i 2 c-bus and how to use it, published by philips. table 11. example i 2 c data transactions master data flow bt819a comment write to bt819a i 2 c start > master sends bt819a chip address, i.e. 0x88 or 0x8a. ack bt819a generates ack on successful receipt of chip address. sub-address > master sends sub-address to bt819a. ack bt819a generates ack on successful receipt of sub-address. data(0) > master sends ?st data byte to bt819a. ack(0) bt819a generates ack on successful receipt of 1st data byte. . . . > > > . . . data(n) > master sends nth data byte to bt819a. ack(n) bt819a generates ack on successful receipt of nth data byte. i 2 c stop master generates stop to end transfer. read from bt819a i 2 c start > master sends bt819a chip address, i.e. 0x89 or 0x8b. ack bt819a generates ack on successful receipt of chip address. < data(0) bt819a sends ?st data byte to master. ack(0) master generates ack on successful receipt of 1st data byte. . . . < < < . . . < data(n-1) bt819a sends (n-1)th data byte to master. ack(n-1) master generates ack on successful receipt of (n-1)th data byte. < data(n) bt819a sends nth data byte to master. no ack master does not acknowledge nth data byte. i 2 c stop master generates stop to end transfer. where: i 2 c start =i 2 c start condition and bt819a chip address (including the r/w bit) sub-address = the 8-bit sub-address of the bt819a register, msb first. data(n) = the data to be transferred to/from the addressed register i 2 c stop =i 2 c stop condition
55 e lectrical i nterfaces i 2 c interface bt819a/7a/5a software reset the contents of the control registers may be reset to their default values by issuing a software reset. a software reset can be accomplished by writing any value to subaddress 0x1f. a read of this location will return an unde?ed value. figure 31. i 2 c protocol diagram chip addr data sa sr a a chip addr sub - addr s a a a a p chip addr sub - addr s a a chip addr a data data data d ata r ead d ata w rite w rite f ollowed by r ead 0 x 89 or 0 x 8b repeated 8 bits f rom m aster to b t 819a f rom b t 819a to m aster s = start sr = repeated start p = stop a = acknowledge na = non acknowledge 0 x 88 or 0 x 8a 0 x 88 or 0 x 8a na p data data a a start aa data data na p data a register pointed to by sub - address
56 e lectrical i nterfaces jtag interface bt819a/7a/5a jtag interface need for functional veri?ation as the complexity of imaging chips increases, the need to easily access individual chips for functional veri?ation is becoming vital. the bt819a has incorporated special circuitry that allows it to be accessed in full compliance with standards set by the joint test action group (jtag). conforming to ieee p1149.1 ?tandard test access port and boundary scan architecture,?the bt819a has dedicated pins that are used for testability purposes only. jtag approach to testability jtags approach to testability utilizes boundary scan cells placed at each digital pin and digital interface (a digital interface is the boundary between an analog block and a digital block within the bt819a). all cells are interconnected into a boundary scan register, as shown in table 12, that applies or captures test data to be used for functional veri?ation of the integrated circuit. jtag is particularly useful for board testers using functional testing methods. jtag consists of ?e dedicated pins comprising the test access port (tap). these pins are test mode select (tms), test clock (tck), test data input (tdi), test data out (tdo) and test reset (trst ). the trst pin will reset the jtag controller when pulled low at any time.veri?ation of the integrated circuit and its connection to other modules on the printed circuit board can be achieved through these ?e tap pins. with boundary scan cells at each digital interface and pin, the bt819a has the capability to apply and capture the respective logic levels. since all of the digital pins are interconnected as a long shift register, the tap logic has ac- cess and control of all the necessary pins to verify functionality. the tap control- ler can shift in any number of test vectors through the tdi input and apply them to the internal circuitry. the output result is scanned out on the tdo pin and exter- nally checked. while isolating the bt819a from other components on the board, the user has easy access to all bt819a digital pins and digital interfaces through the tap and can perform complete functionality tests without using expensive bed-of-nails testers. optional device id register the bt819a has the optional device identi?ation register de?ed by the jtag speci?ation. this register contains information concerning the revision, actual part number, and manufacturers identi?ation code speci? to brooktree. this reg- ister can be accessed through the tap controller via an optional jtag instruction. refer to table 13.
57 e lectrical i nterfaces jtag interface bt819a/7a/5a veri?ation with the tap controller a variety of veri?ation procedures can be performed through the tap controller. with a set of four instructions, the bt819a can verify board connectivity at all dig- ital interfaces and pins. the instructions are accessible by using a state machine standard to all jtag controllers and are: sample/preload, extest, id code, and bypass (see figure 32). refer to the ieee p1149.1 speci?ation for details con- cerning the instruction register and jtag state machine. brooktree has created a bsdl with the at&t bsd editor. table 12 shows the boundary scan de?ition from this ?e. should jtag testing be implemented, a disk with an ascii version of the complete bsdl ?e may be obtained by calling 1-800-2bt apps. table 12. bt819a boundary scan register de?ition (1 of 2) attribute boundary_register of 819a: entity is " 0 (bc_1, *, internal, x)," & " 1 (bc_1, *, control, 1)," & " 2 (bc_1, *, internal, x)," & " 3 (bc_1, *, internal, x)," & " 4 (bc_1, *, internal, x)," & " 5 (bc_1, *, internal, x)," & " 6 (bc_1, *, internal, x)," & " 7 (bc_1, *, internal, x)," & " 8 (bc_1, *, internal, x)," & " 9 (bc_1, *, internal, x)," & " 10 (bc_1, *, internal, 0)," & " 11 (bc_1, *, internal, 0)," & " 12 (bc_1, *, internal, 0)," & " 13 (bc_1, *, internal, 0)," & " 14 (bc_1, *, internal, 0)," & " 15 (bc_1, *, internal, 0)," & " 16 (bc_1, *, internal, 0)," & " 17 (bc_1, *, internal, 0)," & " 18 (bc_1, *, internal, 0)," & " 19 (bc_1, *, internal, 0)," & " 20 (bc_1, *, internal, 0)," & " 21 (bc_1, *, internal, 0)," & " 22 (bc_1, *, internal, 0)," & " 23 (bc_1, *, internal, 0)," & " 24 (bc_1, *, internal, 0)," & " 25 (bc_1, *, control, 0)," & " 26 (bc_1, field, output3, x, 25, 0, z)," & " 27 (bc_1, nvreset, output3, x, 25, 0, z)," & " 28 (bc_1, xtfmt, input, x)," & " 29 (bc_1, nosen, input, x)," & " 30 (bc_1, nhreset, output3, x, 25, 0, z)," & " 31 (bc_1, active, output3, x, 25, 0, z)," & " 32 (bc_1, dvalid, output3, x, 25, 0, z)," & " 33 (bc_1, rden, input, x)," &
58 e lectrical i nterfaces jtag interface bt819a/7a/5a " 34 (bc_1, aff, output3, x, 25, 0, z)," & " 35 (bc_1, aef, output3, x, 25, 0, z)," & " 36 (bc_1, nfrst, input, x)," & " 37 (bc_1, cbflag, output3, x, 25, 0, z)," & " 38 (bc_3, nvsen, input, x)," & " 39 (bc_1, clkin, input, x)," & " 40 (bc_1, qclk, output3, x, 25, 0, z)," & " 41 (bc_1, clkx1, output3, x, 25, 0, z)," & " 42 (bc_1, noe, input, 1)," & " 43 (bc_1, clkx2, output3, x, 25, 0, z)," & " 44 (bc_1, vdb(8), output3, x, 25, 0, z)," & " 45 (bc_1, vdb(9), output3, x, 25, 0, z)," & " 46 (bc_1, vdb(10), output3, x, 25, 0, z)," & " 47 (bc_1, vdb(11), output3, x, 25, 0, z)," & " 48 (bc_1, vdb(12), output3, x, 25, 0, z)," & " 49 (bc_1, vdb(13), output3, x, 25, 0, z)," & " 50 (bc_1, vdb(14), output3, x, 25, 0, z)," & " 51 (bc_1, vdb(15), output3, x, 25, 0, z)," & " 52 (bc_1, *, internal, x)," & " 53 (bc_1, xt0i, input, x)," & " 54 (bc_1, i2ccs, input, x)," & " 55 (bc_1, nrst, input, x)," & " 56 (bc_1, *, internal, x)," & " 57 (bc_1, xt1i, input, x)," & " 58 (bc_1, sda, output3, 1, 58, 1, weak1)," & " 59 (bc_1, sda, input, x)," & " 60 (bc_1, scl, input, x)," & " 61 (bc_1, vda(0), output3, 0, 1, 1, z)," & " 62 (bc_1, vda(0), input, x)," & " 63 (bc_1, vda(1), output3, 0, 1, 1, z)," & " 64 (bc_1, vda(1), input, x)," & " 65 (bc_1, vda(2), output3, 0, 1, 1, z)," & " 66 (bc_1, vda(2), input, x)," & " 67 (bc_1, vda(3), output3, 0, 1, 1, z)," & " 68 (bc_1, vda(3), input, x)," & " 69 (bc_1, vda(4), output3, 0, 1, 1, z)," & " 70 (bc_1, vda(4), input, x)," & " 71 (bc_1, vda(5), output3, 0, 1, 1, z)," & " 72 (bc_1, vda(5), input, x)," & " 73 (bc_1, vda(6), output3, 0, 1, 1, z)," & " 74 (bc_1, vda(6), input, x)," & " 75 (bc_1, vda(7), output3, 0, 1, 1, z)," & " 76 (bc_1, vda(7), input, x)," & " 77 (bc_1, twren, input, x)," & " 78 (bc_0, *, internal, 0)," & " 79 (bc_0, *, internal, 0)"; end 819a; table 12. bt819a boundary scan register de?ition (2 of 2)
59 e lectrical i nterfaces jtag interface bt819a/7a/5a table 13. device identi?ation register note: the part number remains the same for all three parts: bt819a, bt817a and bt815a v ersion p art n umber m anufacturer id xxxx 0000001100110011000110101101 0 0819, 0 x 0333 0 x 0d6 figure 32. instruction register (ir) tdi tdo extest 0 sample/preload 0 id code 0 bypass 1
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61 pc b oard l ayout c onsiderations the layout should be optimized for lowest noise on the bt819a power and ground lines by shielding the digital inputs/outputs and providing good decoupling. the lead length between groups of power and ground pins should be minimized to re- duce inductive ringing. figure 36 shows an example schematic. ground planes the ground plane area should encompass all bt819a ground pins, voltage refer- ence circuitry, power supply bypass circuitry for the bt819a, the analog input trac- es, any input ampli?rs, and all the digital signal traces leading to the bt819a. the bt819a has digital grounds (gnd) and analog grounds (agnd and vneg). the layout for the ground plane should be such that the two planes are at the same electrical potential, but they should be isolated from each other in the ar- eas surrounding the chip. also, the return path for current should be through the digital plane. see figure 33. figure 33. example ground plane layout bt819a 1 50 a nalog g round d igital g round g round r eturn ( i . e . isa b us c onnection ) c ircuit board edge
62 pc b oard l ayout c onsiderations power planes bt819a/7a/5a power planes the power plane area should encompass all bt819a power pins, voltage reference circuitry, power supply bypass circuitry for the bt819a, the analog input traces, any input ampli?rs, and all the digital signal traces leading to the bt819a. the bt819a has digital power (vdd) and analog power (vaa and vpos). the layout for the power plane should be such that the two planes are at the same elec- trical potential, but they should be isolated from each other in the areas surround- ing the chip. also, the return path for current should be through the digital plane. this is the same layout as shown for the ground plane (figure 33). when using a regulator, circuitry must be included to ensure proper power sequencing. the cir- cuitry shown in figure 34 should help in this regard. supply decoupling the bypass capacitors should be installed with the shortest leads possible, consis- tent with reliable operation, to reduce the lead inductance. these capacitors should also be placed as close as possible to the device. each group of vaa and vdd pins should have a 0.1 m f ceramic bypass capac- itor to ground, located as close as possible to the device. additionally, 10 m f capacitors should be connected between the analog power and ground planes, as well as between the digital power and ground planes. these capacitors are at the same electrical potential, but provide additional decoupling by being physically close to the bt819a power and ground planes. see figure 35 for additional information about power supply decoupling. digital signal interconnect the digital signals of the bt819a should be isolated as much as possible from the analog signals and other analog circuitry. also, the digital signals should not over- lay the analog power plane. any termination resistors for the digital signals should be connected to the reg- ular pcb power and ground planes. analog signal interconnect long lengths of closely-spaced parallel video signals should be avoided to mini- mize crosstalk. ideally, there should be a ground line between the video signal trac- es driving the yin and cin inputs. also, high-speed ttl signals should not be routed close to the analog signals to minimize noise coupling. latch-up avoidance latch-up is a failure mechanism inherent to any cmos device. it is triggered by static or impulse voltages on any signal input pin exceeding the voltage on the power pins by more than 0.5 v, or falling below the gnd pins by more than 0.5 v. latch-up can also occur if the voltage on any power pin exceeds the voltage on any other power pin by more than 0.5 v. in some cases, devices with mixed signal interfaces, such as the bt819a, can appear more sensitive to latch-up. in reality, this is not the case. however, mixed signal devices tend to interact with peripheral devices such as video monitors or cameras that are referenced to different ground potentials, or apply voltages to the device prior to the time that its power system is stable. this interaction sometimes creates conditions amenable to the onset of latch-up.
63 pc b oard l ayout c onsiderations latch-up avoidance bt819a/7a/5a to maintain a robust design with the bt819a, the following precautions should be taken: apply power to the device before or at the same time as the interface cir- cuitry. do not apply voltages below gnd?.5 v, or higher than vaa+0.5 v to any pin on the device. do not use negative supply op-amps or any other negative voltage interface circuitry. all logic inputs should be held low until power to the device has settled to the speci?d tolerance. connect all vdd, vaa and vpos pins together through a low imped- ance plane. connect all gnd, agnd and vneg pins together through a low imped- ance plane. figure 34. optional regulator circuitry i n s ystem p ower vaa,vdd o ut g round gnd s uggested part numbers : r egulator t exas i nstruments m a78 mo5m (+5 v) s ystem p ower (+5 v) (+12 v) d iodes must handle of the bt819a and the peripheral circuitry the current requirements
64 pc b oard l ayout c onsiderations schematics bt819a/7a/5a schematics figure 35. typical power and ground connection diagram and parts list +5 v (vcc) g round + + c1 c2 c3 c4 c5 c6 vdd vaa, vpos gnd, agnd, vneg bt819a location description vendor part number c1, c2, c3, c4 (1) 0.1 m f ceramic capacitor erie rpe112z5u104m50v (3) c5, c6 (2) 10 m f tantalum capacitor mallory csr13g106km (3) notes: (1). a 0.1 m f capacitor should be connected between each group of power pins and ground as close to the device as possible, (ceramic chip capacitors are preferred). (2). the 10 m f capacitors should be connected between the analog supply and the analog ground, as well as the digital supply and the digital ground. these should be connected as close to the bt819a as possible. (3). these vendor numbers are listed only as a guide. substitution of devices with similar characteristics will not affect the performance of the bt819a.
65 pc b oard l ayout c onsiderations schematics bt819a/7a/5a figure 36. example schematic y1 y0 crcb7 crcb6 crcb5 crcb4 crcb3 crcb2 y7 y6 y5 y4 y3 y2 cc1 30k r56 1 2 r119 30k a c109 0.1uf 1 2 c d 0.1uf c55 0.1uf c43 vaa c42 0.1uf r63 2k c106 0.1uf 1m r120 vaa luma data chroma data vaa vdd c18 0.1uf 0.1uf c19 u1 rst oe frst yref- yref+ yin ydbias ycbias yabias vpos vneg vd9 vd8 vd7 vd6 vd5 vd4 vd3 v d2 vd15 vd14 vd13 vd12 vd11 vd10 vaa4 vaa3 vaa2 vaa1 vaa0 syncdet sda scl refout rden n/c_1 muxout mux1 mux0 i2ccs cref- cref+ clevel cin cdbias ccbias cabias agnd7 agnd6 agnd5 agnd4 agnd3 agnd2 agnd1 agnd0 agccap 15 98 88 62 49 52 50 46 51 40 42 8 9 22 23 24 25 26 27 2 3 4 5 6 7 72 65 60 48 44 59 18 19 43 85 68 53 57 55 14 73 64 74 67 63 69 70 75 71 66 61 58 56 54 47 41 mux2 45
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67 c ontrol r egister d efinitions the following tables describe the function of the various control registers. the section begins with a summary of the register functions and follows with details of each register. register name mnemonic register address 640 x 480 square pixel ntsc (default) 768 x 576 square pixel pal 720 x 480 ccir ntsc 720 x 576 ccir pal 360 x 240 2:1 ccir ntsc (single field, cif) 360 x 288 2:1 ccir pal (single field, cif) device status status 0x00 0x00 0x00 0x00 0x00 0x00 0x00 input format iform 0x01 0x58 0x78 0x58 0x78 0x58 0x78 temporal decimation tdec 0x02 0x00 0x00 0x00 0x00 0x00 0x00 msb cropping crop 0x03 0x12 0x23 0x12 0x22 0x11 0x21 vertical delay, lower byte vdelay_lo 0x04 0x16 0x16 0x16 0x16 0x16 0x16 vertical active, lower byte vactive_lo 0x05 0xe0 0x40 0xe0 0x40 0xe0 0x40 horizontal delay, lower byte hdelay_lo 0x06 0x78 0x9a 0x80 0x90 0x38 0x48 horizontal active, lower byte hactive_lo 0x07 0x80 0x00 0xd0 0xd0 0x40 0x0c horizontal scaling, upper byte hscale_hi 0x08 0x02 0x03 0x00 0x05 0x11 0x1a horizontal scaling, lower byte hscale_lo 0x09 0xaa 0x3c 0xf8 0x04 0xf0 0x09 brightness control bright 0x0a 0x00 0x00 0x00 0x00 0x00 0x00 miscellaneous control control 0x0b 0x20 0x20 0x20 0x20 0x20 0x20 luma gain, lower byte (contrast) contrast_lo 0x0c 0xd8 0xd8 0xd8 0xd8 0xd8 0xd8 chroma (u) gain, lower byte (saturation) sat_u_lo 0x0d 0xfe 0xfe 0xfe 0xfe 0xfe 0xfe chroma (v) gain, upper byte (saturation) sat_v_lo 0x0e 0xb4 0xb4 0xb4 0xb4 0xb4 0xb4 hue control hue 0x0f 0x00 0x00 0x00 0x00 0x00 0x00 reserved 0x10 0x00 0x00 0x00 0x00 0x00 0x00 reserved 0x11 0x00 0x00 0x00 0x00 0x00 0x00
68 c ontrol r egister d efinitions 0x00 ?device status register (status) bt819a/7a/5a 0x00 ?device status register (status) this control register may be written to or read by the mpu at any time. upon reset it is initialized to 0x00. cof is the least signi?ant bit. an asterisk indicates the default option. the cof and lof status bits hold their values until reset to their default values by writing to them. the other six bits do not hold their values, but continually output the status. pres video present status. video is determined as present when an input signal is deter- mined to have a signal above one half the sync height for 31 consecutive clock cy- cles. in the presence of video, this bit is set to a logical one. it can be reset to zero by writing a logical zero to this bit. due to the nature of the agc circuitry, it is pos- sible that noise could induce this bit to be set. therefore, it can not be used for pre- cise determination of the presence of a video source. 0* = video not present 1 = video present output format oform 0x12 0x06 0x06 0x06 0x06 0x06 0x06 vertical scaling, upper byte vscale_hi 0x13 0x60 0x60 0x60 0x60 0x60 0x60 vertical scaling, lower byte vscale_lo 0x14 0x00 0x00 0x00 0x00 0x00 0x00 test control test 0x15 0x00 0x00 0x00 0x00 0x00 0x00 video timing polarity register vpole 0x16 0x00 0x00 0x00 0x00 0x00 0x00 id code idcode 0x17 0x70 0x70 0x70 0x70 0x70 0x70 agc delay adelay 0x18 0x68 0x7f 0x68 0x7f 0x68 0x7f burst gate delay bdelay 0x19 0x5d 0x72 0x5d 0x72 0x5d 0x72 adc interface adc 0x1a 0x82 0x82 0x82 0x82 0x82 0x82 reserved 0x1b- 0x1e software reset sreset 0x1f register name mnemonic register address 640 x 480 square pixel ntsc (default) 768 x 576 square pixel pal 720 x 480 ccir ntsc 720 x 576 ccir pal 360 x 240 2:1 ccir ntsc (single field, cif) 360 x 288 2:1 ccir pal (single field, cif) 7 6 5 4 3 2 1 0 pres hloc field numl csel reserved lof cof 00000000
69 c ontrol r egister d efinitions 0x00 ?device status register (status) bt819a/7a/5a hloc device in h-lock. if hsync is found within 1 clock cycle of the expected posi- tion of hsync for 32 consecutive lines, this bit is set to a logical 1. once set, if hsync is not found within 1 clock cycle of the expected position of hsync for 32 consecutive lines, this bit is set to a logical 0. mpu writes to this bit are ignored. this bit indicates the stability of the incoming video. while it is an indicator of horizontal locking, some video sources will characteristically vary from line to line by more than one clock cycle so that this bit will never be set. consumer vcrs are examples of sources that will tend to never set this bit. 0* = device not in h-lock 1 = device in h-lock field field status. this bit re?cts whether an odd or even ?ld is being decoded. the field bit is determined by the relationship between hreset and vreset . 0* = odd ?ld 1 = even ?ld numl number of lines. this bit identi?s the number of lines found in the video stream. this bit is used to determine the type of video input to the bt819a. thirty-two con- secutive ?lds with the same number of lines is required before this status bit will change. 0* = 525 line format (ntsc) 1 = 625 line format (pal) csel crystal select. this bit identi?s which crystal port is selected. when automatic format detection is enabled, this bit will be the same as numl. 0* = xtal0 input selected 1 = xtal1 input selected reserved this bit should only be written with a logical zero. lof luma adc over?w. on power-up, this bit is set to 0. if an adc over?w occurs, the bit is set to a logical 1. it is reset after being written to or a chip reset occurs. if an over?w occurs in the luma adc, the clamp level used for agc may be adjust- ed by programming the clamp bits in the adc register (0x1a). this is bene?ial if the amplitude of the video signal is not accurate with respect to the sync height. the state of this bit is not valid and should be ignored when the adc is in pow- er-down mode (y_sleep = 1). when the luma a/d is in sleep mode, lof is set to 1. cof chroma adc over?w. on power-up, this bit is set to 0. if an adc over?w oc- curs, the bit is set to a logical 1. it is reset after being written to or a chip reset oc- curs. the state of this bit is not valid and should be ignored when the adc is in power-down mode (c_sleep = 1). when the chroma a/d is in sleep mode, cof is set to 1. reads from this bit are insigni?ant on the bt815a.
70 c ontrol r egister d efinitions 0x01 ?input format register (iform) bt819a/7a/5a 0x01 ?input format register (iform) this control register may be written to or read by the mpu at any time. upon reset it is initialized to 0x58. format(0) is the least signi?ant bit. an asterisk indicates the default option. hactive when using the bt819a with a packed memory architecture, for example, with ?ld memories, this bit should be programmed with a logical 1. when implement- ing a vram based architecture, program with a logical 0. 0* = reset hactive with hreset 1 = extend hactive beyond hreset muxsel used for software control of video input selection. the bt819a can select between two composite video sources, or one composite and one s-video source. 00 = reserved 01 = select mux2 input to muxout 10* = select mux0 input to muxout 11 = select mux1 input to muxout xtsel if automatic format detection is required, logical 11 must be loaded. logical 01 and 10 are used if software format selection is desired. 00 = reserved 01 = select xt0 input (only xt0 present) 10 = select xt1 input (both xts present) 11* = auto xt select enabled (both xts present) reserved this bit should only be written with a logical zero. format automatic format detection may be enabled or disabled. the numl bit is used to determine the input format when automatic format detection is enabled. 00* = auto format detect enabled 01 = ntsc (m) input format 10 = reserved 11 = pal (b, d, g, h, i) input format 7 6 5 4 3 2 1 0 hactive muxsel xtsel reserved format 01011000
71 c ontrol r egister d efinitions 0x02 ?temporal decimation register (tdec) bt819a/7a/5a 0x02 ?temporal decimation register (tdec) this control register may be written to or read by the mpu at any time. upon reset it is initialized to 0x00. dec_rat(0) is the least signi?ant bit. an asterisk indicates the default option. this register enables temporal dec- imation by discarding a ?ite number of ?lds or frames from the incoming video. dec_field de?es whether decimation is by ?lds or frames. 0* = decimate frames 1 = decimate ?lds dec_rat dec_rat is the number of ?lds or frames dropped out of 60 (ntsc) or 50 (pal) ?lds or frames. 0x00 value disables decimation (all video frames and ?lds are output). caution: when changing the programming in the tdec register, 0x00 must be loaded ?st and then the decimation value. this will ensure decimation does not start on the wrong ?ld or frame. the register should not be loaded with greater than 60 (0x3c) for ntsc, or 50 (0x34) for pal. 0x00?xff = number of ?lds / frames output. 7 6 5 4 3 2 1 0 dec_field dec_rat 00000000
72 c ontrol r egister d efinitions 0x03 ?msb cropping register (crop) bt819a/7a/5a 0x03 ?msb cropping register (crop) this control register may be written to or read by the mpu at any time. upon reset it is initialized to 0x12. hactive_msb(0) is the least signi?ant bit. see the vactive, vdelay, hactive and hdelay registers for descriptions on the operation of this register. vdelay_msb 00xx xxxx?1xx xxxx = the most signi?ant two bits of vertical delay register vactive_msb xx00 xxxx?x11 xxxx = the most signi?ant two bits of vertical active register hdelay_msb xxxx 00xx?xxx 11xx = the most signi?ant two bits of horizontal delay register hactive_msb xxxx xx00?xxx xx11 = the most signi?ant two bits of horizontal active register 0x04 ?vertical delay register, lower byte (vdelay_lo) this control register may be written to or read by the mpu at any time. upon reset it is initialized to 0x16. vdelay_lo(0) is the least signi?ant bit. this 8-bit register is the lower byte of the 10-bit vdelay register. the two msbs of vdelay are contained in the crop register. vdelay de?es the number of half lines between the trailing edge of vreset and the start of active video. vdelay_lo 0x01?xff = the least signi?ant byte of the vertical delay register. 7 6 5 4 3 2 1 0 vdelay_msb vactive_msb hdelay_msb hactive_msb 00010010 7 6 5 4 3 2 1 0 vdelay_lo 00010110
73 c ontrol r egister d efinitions 0x05 ?vertical active register, lower byte (vactive_lo) bt819a/7a/5a 0x05 ?vertical active register, lower byte (vactive_lo) this control register may be written to or read by the mpu at any time, and upon reset it is initialized to 0xe0. vactive_lo(0) is the least signi?ant bit. this 8-bit register is the lower byte of the 10-bit vactive register. the two msbs of vactive are contained in the crop register. vactive de?es the number of lines used in the ver- tical scaling process. the actual number of lines output by the bt819a is scaling_ratio * vactive. vactive_lo 0x00?xff = the least signi?ant byte of the vertical active register. 0x06 ?horizontal delay register, lower byte (hdelay_lo) this control register may be written to or read by the mpu at any time. upon reset it is initialized to 0x78. hdelay_lo(0) is the least signi?ant bit. this 8-bit register is the lower byte of the 10-bit hdelay register. the two msbs of hdelay are contained in the crop register. hdelay de?es the number of scaled pixels between the falling edge of hreset and the start of active video. hdelay_lo 0x01?xff = the least signi?ant byte of the horizontal delay register. hactive pixels will be output by the chip starting at the fall of hreset. caution: hdelay must be programmed with an even number. 0x07 ?horizontal active register, lower byte (hactive_lo) this control register may be written to or read by the mpu at any time. upon reset it is initialized to 0x80. hactive_lo(0) is the least signi?ant bit. hactive de?es the number of horizontal active pixels per line output by the bt819a. hactive_lo 0x00?xff = the least signi?ant byte of the horizontal active register. this 8-bit register is the lower byte of the 10-bit hactive register. the two msbs of hac- tive are contained in the crop register. 7 6 5 4 3 2 1 0 vactive_lo 11100000 7 6 5 4 3 2 1 0 hdelay_lo 01111000 7 6 5 4 3 2 1 0 hactive_lo 10000000
74 c ontrol r egister d efinitions 0x08 ?horizontal scaling register, upper byte (hscale_hi) bt819a/7a/5a 0x08 ?horizontal scaling register, upper byte (hscale_hi) this control register may be written to or read by the mpu at any time. upon reset it is initialized to 0x02. this 8-bit register is the upper byte of the 16-bit hscale register. hscale_hi 0x00?xff = the most signi?ant byte of the horizontal scaling ratio 0x09 ?horizontal scaling register, lower byte (hscale_lo) this control register may be written to or read by the mpu at any time. upon reset it is initialized to 0xac. this 8-bit register is the lower byte of the 16-bit hscale register. hscale_lo 0x00?xff = the least signi?ant byte of the horizontal scaling ratio 7 6 5 4 3 2 1 0 hscale_hi 00000010 7 6 5 4 3 2 1 0 hscale_lo 10101100
75 c ontrol r egister d efinitions 0x0a ?brightness control register (bright) bt819a/7a/5a 0x0a ?brightness control register (bright) the brightness control involves the addition of a twos complement number to the luma channel. brightness can be adjusted in 255 steps, from ?28 to +127. the resolution of brightness change is one lsb (0.39% with respect to the full luma range). bright 7 6 5 4 3 2 1 0 bright 00000000 hex value binary value brightness changed by number of lsbs percent of full scale 0x80 1000 0000 ?28 ?0% 0x81 1000 0001 ?27 ?9.6% . . . . . . 0xff 1111 1111 ?1 ?.39% 0x00* 0000 0000* 00 0% 0x01 0000 0001 +01 +0.39% . . . . . . 0x7e 0111 1110 +126 +49.2% 0x7f 0111 1111 +127 +49.6%
76 c ontrol r egister d efinitions 0x0b ?miscellaneous control register (control) bt819a/7a/5a 0x0b ?miscellaneous control register (control) this control register may be written to or read by the mpu at any time, and upon reset it is initialized to 0x20. sat_v_msb is the least signi?ant bit. lnotch this bit is used to include the luma notch ?ter. for monochrome video, the notch should not be used. this will output full bandwidth luminance. 0* = enable the luma notch ?ter 1 = disable the luma notch ?ter comp when comp is set to logical one, the luma notch is disabled. when comp is set to logical zero, the c adc is disabled. when using the bt815a, this bit must be programmed with a zero. ** bt819a and bt817a only. 0* = composite video 1 = y/c component video ldec the luma decimation ?ter is used to reduce the high-frequency component of the luma signal. useful when scaling to cif resolutions or lower. 0 = enable luma decimation 1* = disable luma decimation cbsense this bit controls whether the ?st pixel of a line is a cb pixel or a cr pixel. for ex- ample, if cbsense is low and hdelay is an even number, the ?st active pixel output is a cb pixel. if hdelay is odd, cbsense may be programmed high to produce a cb pixel as the ?st active pixel output. 0* = normal cbflag (high for the 1st pixel of line) 1 = invert the cbflag polarity interp this is primarily a test mode. the interpolator should always be enabled. 0* = enable interpolation 1 = disable interpolation con_msb the most signi?ant bit of the luma gain (contrast) value sat_u_msb the most signi?ant bit of the chroma (u) gain value sat_v_msb the most signi?ant bit of the chroma (v) gain value 7 6 5 4 3 2 1 0 lnotch comp** ldec cbsense interp con_msb sat_u_msb sat_v_msb 001000 0 0
77 c ontrol r egister d efinitions 0x0c ?luma gain register, lower byte (contrast_lo) bt819a/7a/5a 0x0c ?luma gain register, lower byte (contrast_lo) this control register may be written to or read by the mpu at any time. upon reset it is initialized to 0xd8. contrast_lo(0) is the least signi?ant bit. the con_l_msb bit and the contrast_lo register concatenate to form the 9-bit contrast register. the value in this register is multiplied by the luminance value to provide con- trast adjustment. contrast_lo the least signi?ant byte of the luma gain (contrast) value. 7 6 5 4 3 2 1 0 contrast_lo 11011000 decimal value hex value % of original signal 511 0x1ff 236.57% 510 0x1fe 236.13% . . . . . . 217 0x0d9 100.46% 216 0x0d8* 100.00% . . . . . . 128 0x080 59.26% . . . . . . 1 0x001 0.46% 0 0x000 0.00%
78 c ontrol r egister d efinitions 0x0d ?chroma (u) gain register, lower byte (sat_u_lo) bt819a/7a/5a 0x0d ?chroma (u) gain register, lower byte (sat_u_lo) this control register may be written to or read by the mpu at any time. upon reset it is initialized to 0xfe. sat_u_lo(0) is the least signi?ant bit. sat_u_msb in the control register, and sat_u_lo concatenate to give a 9-bit register (sat_u). this register is used to add a gain adjustment to the u component of the video signal. by adjusting the u and v color components of the video stream by the same amount, the saturation is adjusted. for normal saturation adjustment, the gain in both the color difference paths must be the same (i.e. the ratio between the value in the u gain register and the value in the v gain register should be kept constant at the default power-up ratio). when changing the saturation, if the sat_u_msb bit is altered, care must be taken to ensure that the other bits in the control register are not affected. sat_u_lo 7 6 5 4 3 2 1 0 sat_u_lo 11111110 decimal value hex value % of original signal 511 0x1ff 201.18% 510 0x1fe 200.79% . . . . . . 255 0x0ff 100.39% 254 0x0fe* 100.00% . . . . . . 128 0x080 50.39% . . . . . . 1 0x001 0.39% 0 0x000 0.00%
79 c ontrol r egister d efinitions 0x0e ?chroma (v) gain register, lower byte (sat_v_lo) bt819a/7a/5a 0x0e ?chroma (v) gain register, lower byte (sat_v_lo) this control register may be written to or read by the mpu at any time. upon reset it is initialized to 0xb4. sat_v_lo(0) is the least signi?ant bit. sat_v_msb in the control register and sat_v_lo concatenate to give a 9-bit register (sat_v). this register is used to add a gain adjustment to the v component of the video signal. by adjusting the u and v color components of the video stream by the same amount, the saturation is adjusted. for normal saturation adjustment, the gain in both the color difference paths must be the same (i.e. the ratio between the value in the u gain register and the value in the v gain register should be kept constant at the default power-up ratio). when changing the saturation, if the sat_v_msb bit is altered, care must be taken to ensure that the other bits in the control register are not affected. sat_v_lo 7 6 5 4 3 2 1 0 sat_v_lo 10110100 decimal value hex value % of original signal 511 0x1ff 283.89% 510 0x1fe 283.33% . . . . . . 181 0x0b5 100.56% 180 0x0b4* 100.00% . . . . . . 128 0x080 71.11% . . . . . . 1 0x001 0.56% 0 0x000 0.00%
80 c ontrol r egister d efinitions 0x0f ?hue control register (hue) bt819a/7a/5a 0x0f ?hue control register (hue) this control register may be written to or read by the mpu at any time. upon reset it is initialized to 0x00. hue(0) is the least signi?ant bit. an asterisk indicates the default option. hue adjustment involves the addition of a twos complement number to the demodulating subcarrier phase. hue can be adjusted in 256 steps in the range ?0? to +89.3?, in increments of 0.7?. hue 7 6 5 4 3 2 1 0 hue 00000000 hex value binary value subcarrier reference changed by resulting hue changed by 0x80 1000 0000 ?0? +90? 0x81 1000 0001 ?9.3? +89.3? . . . . . . . . 0xff 1111 1111 ?.7? +0.7? 0x00* 0000 0000* 00? 00? 0x01 0000 0001 +0.7? ?.7? . . . . . . . . 0x7e 0111 1110 +88.6? ?8.6? 0x7f 0111 1111 +89.3? ?9.3?
81 c ontrol r egister d efinitions 0x10 ?reserved bt819a/7a/5a 0x10 ?reserved this control register may be written to or read by the mpu at any time. upon reset it is initialized to 0x00, and must only be written to with 0x00. 0x11 ?reserved this control register may be written to or read by the mpu at any time. upon reset it is initialized to 0x00, and must only be written to with 0x00.
82 c ontrol r egister d efinitions 0x12 ?output format register (oform) bt819a/7a/5a 0x12 ?output format register (oform) this control register may be written to or read by the mpu at any time. upon reset it is initialized to 0x06. full is the least signi?ant bit. an asterisk indicates the default option. range luma output range: this bit determines the range for the luminance output on the bt819a. the range must be limited when using the control codes as video timing. 0* = normal operation (luma range 16?53, chroma range 2?53). y=16 is black (pedestal). cr, cb=128 is zero color information. 1 = full-range output (luma range 0?55, chroma range 2?53) y=0 is black (pedestal). cr, cb=128 is zero color information. rnd output rounding: these bits control the number of bits output from the bt819a, msb justi?d. when rounding is implemented, the unused lsbs are set to zero. 00* = normal operation 01 = 6-bit luma & 4-bit chroma output (rounded) 10 = 7-bit luma & 5-bit chroma output (rounded) 11 = reserved fifo_burst fifo read control: when enabled, this pin internally connects rden to dvalid. in api mode, when these pins are connected, the data is automatically burst out of the fifo. if these pins are not connected, the system must control reads from the fifo, and ensure the data does not over?w. reads and writes to this bit are ignored on the bt817a and bt815a. ** applies only to bt819a. 0* = internally feedback dvalid to rden 1 = control rden externally code code control disable: this bit determines if control codes are output with the vid- eo data. spi mode 2 requires this bit to be programmed with a logical 1. when con- trol codes are inserted into the data stream, the external control signals are still available. 0* = disable control code insertion 1 = enable control code insertion 7 6 5 4 3 2 1 0 range rnd fifo_burst** code len spi** full 000 0 0110
83 c ontrol r egister d efinitions 0x12 ?output format register (oform) bt819a/7a/5a len eight or sixteen bit format: this bit determines the output data format. in 8-bit mode, the data is output on vd[15:8]. 0 = 8-bit ycrcb 4:2:2 output stream 1* = 16-bit ycrcb 4:2:2 output stream spi pixel interface control: when programmed with a logical zero, the data is output using the fifo in api mode. when programmed with a logical one, the fifo is bypassed and the data is output in spi mode. on the bt817a and bt815a, this bit must be loaded with a logical one. ** applies only to bt819a. 0 = asynchronous pixel interface 1* = synchronous pixel interface full this bit controls the point at which the fifo full ?g toggles. when programmed with a logical zero, the fifo signals that it is half full by setting aff high at 20 pixels (out of a possible 40). when programmed with a logical one, aff toggles high at 32 pixels indicating that the fifo is approaching full. writes and reads to this pin are ignored on the bt817a and bt815a. 0* = aff and dvalid go high when there are at least 20 pixels in the output fifo. 1 = aff and dvalid go high when there are at least 32 pixels in the output fifo. y/cr/cb[7] y/cr/cb[0] y[7] y[0] vd[15] vd[8] vd[7] vd[0] cr/cb[7] cr/cb[0] vd 16-bit 8-bit
84 c ontrol r egister d efinitions 0x13 ?vertical scaling register, upper byte (vscale_hi) bt819a/7a/5a 0x13 ?vertical scaling register, upper byte (vscale_hi) this control register may be written to or read by the mpu at any time. upon reset it is initialized to 0x60. line line store enable: this bit enables operation of the line store for use in vertical scaling. when enabled, the luminance component of the video signal is scaled us- ing two-tap, poly-phase scaling. when disabled, simple line dropping is imple- mented. reads and writes to this bit are ignored on the bt817a and bt815a. ** applies to bt819a only. 0* = luma vs using line store 1 = luma vs using dda comb chroma comb enable: this bit determines if the chroma comb is included in the data path. if enabled, a full line store is used to average adjacent lines of color in- formation, reducing cross-color artifacts. the chroma comb is available on all three parts (bt819a, bt817a and bt815a). 0 = chroma comb disabled 1* = chroma comb enabled int interlace: this bit is programmed to indicate if the incoming video is interlaced or non-interlaced. for example, if using the full frame as input for vertical scaling, this bit should be programmed high. if using a single ?ld for vertical scaling, this bit should be programmed low. single ?ld scaling is normally used when scaling below cif resolution and outputting to a non-interlaced monitor. using a single ?ld will reduce motion artifacts. 0 = non-interlace vs 1* = interlace vs vscale_hi vertical scaling ratio: these ?e bits represent the most signi?ant portion of the 13-bit vertical scaling ratio register. the system must take care not to alter the con- tents of the line, comb and int bits while adjusting the scaling ratio. 7 6 5 4 3 2 1 0 line** comb int vscale_hi 01100000
85 c ontrol r egister d efinitions 0x14 ?vertical scaling register, lower byte (vscale_lo) bt819a/7a/5a 0x14 ?vertical scaling register, lower byte (vscale_lo) this control register may be written to or read by the mpu at any time. upon reset it is initialized to 0x00. vscale_lo vertical scaling ratio: these eight bits represent the least signi?ant byte of the 13-bit vertical scaling ratio register. they are concatenated with ?e bits in vscale_hi. the following equation should be used to determine the value for this register: for example, to scale pal input to square pixel qcif, the total number of vertical lines is 156: 7 6 5 4 3 2 1 0 vscale_lo 00000000 vscale = ( 0x10000 ?{ [ ( scaling_ratio ) ?1] * 512 } ) & 0x1fff vscale = ( 0x10000 ?{ [ ( 4/1 ) - 1 ] * 512 } ) & 0x1fff = 0x1a00
86 c ontrol r egister d efinitions 0x15 ?test control register (test) bt819a/7a/5a 0x15 ?test control register (test) this control register is reserved for putting the part into test mode. write operation to this register may cause unde- termined behavior and should not be attempted. a read cycle from this register returns 0x01, and only a write of 0x01 is permitted. 0x16 ?video timing polarity register (vpole) this control register may be written to or read by the mpu at any time. upon reset, it is initialized to 0x00. outen three-states the following pins: vd[15:0], hreset , vreset , active, dvalid, cbflag, field, aef, aff, qclk, clkx1, and clkx2. 0* = enable outputs 1 = three-stated outputs dvalid 0* = dvalid pin: active high 1 = dvalid pin: active low aff ** this bit applies only to the bt819a. reads and writes to this bit are ignored on the bt817a and bt815a. 0* = aff pin: active high 1 = aff pin: active low cbflag 0* = cbflag pin: active high 1 = cbflag pin: active low field 0* = field pin: high indicates odd ?ld 1 = field pin: high indicates even ?ld active 0* = active pin: active high 1 = active pin: active low hreset 0* = hreset pin: active low 1 = hreset pin: active high vreset 0* = vreset pin: active low 1 = vreset pin: active high note: in api mode, the field, valid and aff pins do not have programmable polar- ities. they are programmable only in spi mode. 7 6 5 4 3 2 1 0 out_en dvalid aff** cbflag field active hreset vreset 00000000
87 c ontrol r egister d efinitions 0x17 ?id code register (idcode) bt819a/7a/5a 0x17 ?id code register (idcode) this control register may be read by the mpu at any time. idcode(0) is the least signi?ant bit. part_id part_rev 0x0 ?0xf = current revision id code 0x18 ?agc delay register (adelay) this control register may be written to or read by the mpu at any time. upon reset, it is initialized to 0x68. adelay agc gate delay for back-porch sampling. the following equation should be used to determine the value for this register: for example, for an ntsc input signal: 7 6 5 4 3 2 1 0 part_id part_rev 01110000 0111 bt819a part id code 0110 bt817a part id code 0010 bt815a part id code 7 6 5 4 3 2 1 0 adelay 01101000 adelay = ( 6.8 m s * f clkx1 ) + 7 adelay = ( 6.8 m s * 14.32 mhz ) + 7 = 104 (0x68)
88 c ontrol r egister d efinitions 0x19 ?burst delay register (bdelay) bt819a/7a/5a 0x19 ?burst delay register (bdelay) this control register may be written to or read by the mpu at any time. upon reset, it is initialized to 0x5d. bdelay(0) is the least signi?ant bit. bdelay the burst gate delay for sub-carrier sampling. the following equation should be used to determine the value for this register: for example, for an ntsc input signal: 7 6 5 4 3 2 1 0 bdelay 01011101 bdelay = ( 6.5 m s * f clkx1 ) bdelay = ( 6.5 m s * 14.32 mhz ) = 93 (0x5d)
89 c ontrol r egister d efinitions 0x1a ?adc interface register (adc) bt819a/7a/5a 0x1a ?adc interface register (adc) this control register may be written to or read by the mpu at any time. upon reset, it is initialized to 0x82. adc(0) is the least signi?ant bit. clamp 00 = clamp on the back porch to 0x30 01 = clamp on the back porch to 0x34 10* = clamp on the back porch to 0x38 11 = clamp on the back porch to 0x3c sync_t 0* = analog syncdet threshold high (~125 mv) 1 = analog syncdet threshold low (~75 mv) agc_en 0* = agc enabled 1 = agc disabled clk_sleep output clocks are still running, i 2 c registers are still accessible. recovery time is approximately one second. 0* = normal clock operation 1 = shut down the system clock (power down) y_sleep 0* = normal y adc operation 1 = sleep y adc operation c_sleep ** applies only to bt819a and bt817a. reads and writes to this bit are ignored on bt815a. 0 = normal c adc operation 1* = sleep c adc operation reserved this bit should only be written with a logical zero. 7 6 5 4 3 2 1 0 clamp sync_t agc_en clk_sleep y_sleep c_sleep** reserved 10000010
90 c ontrol r egister d efinitions 0x1b to 0x1e ?reserved registers bt819a/7a/5a 0x1b to 0x1e ?reserved registers these control registers are reserved for future use. write operations to these registers may cause undetermined be- havior and should not be attempted. a read cycle from these registers returns an unde?ed value. 0x1f ?software reset register (sreset) this command register can be written at any time. read cycles to this register return an unde?ed value. a data write cycle to this register resets the device to the default state (indicated in the command register de?itions by an aster- isk). writing any data value into this address resets the device.
91 p arametric i nformation dc electrical parameters table 14. recommended operating conditions parameter symbol min typ max units power supply ?analog v aa 4.75 5.00 5.25 v power supply ?digital v dd 4.75 5.00 5.25 v maximum d |v dd ?v aa | 0.5 v mux0, mux1 and mux2input range (ac coupling required) 0.5 1.00 2.00 v vin amplitude range (ac coupling required) 0.5 1.00 2.00 v ambient operating temperature t a 0 +70 ?c table 15. absolute maximum ratings parameter symbol min typ max units v aa (measured to agnd) 7.00 v v dd (measured to dgnd) 7.00 v voltage on any signal pin (see the note below) dgnd ?0.5 v dd + 0.5 v analog input voltage agnd ?0.5 v aa + 0.5 v storage temperature t s ?5 +150 ?c junction temperature t j +125 ?c vapor phase soldering (15 seconds) t vsol +220 ?c note: stresses above those listed may cause permanent damage to the device. this is a stress rating only, and func- tional operation at these or any other conditions above those listed in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. this device employs high-impedance cmos devices on all signal pins. it must be handled as an esd-sensi- tive device. voltage on any signal pin that exceeds the power supply voltage by more than +0.5 v or drops below ground by more than 0.5 v can induce destructive latchup.
92 p arametric i nformation ac electrical parameters bt819a/7a/5a ac electrical parameters table 16. dc characteristics parameter symbol min typ max units digital inputs input high voltage (ttl) input low voltage (ttl) input high voltage (xt0i, xt1i) input low voltage (xt0i, xt1i) input high current (v in =v dd ) input low current (v in =gnd) input capacitance (f=1 mhz, v in =2.4 v) v ih v il v ih v il i ih i il c in 2.0 3.5 gnd ?0.5 5 v dd + 0.5 0.8 v dd + 0.5 1.5 10 ?0 v v v v m a m a pf digital outputs output high voltage (i oh = ?00 m a) output low voltage (i ol = 3.2 ma) 3-state current output capacitance v oh v ol i oz c o 2.4 5 v dd 0.4 10 v v m a pf analog pin input capacitance c a 5pf table 17. clock timing parameters parameter symbol min typ max units ntsc: clkx1 rate clkx2 rate (50 ppm source required) f s1 f s2 14.318181 28.636363 mhz mhz pal: clkx1 rate clkx2 rate (50 ppm source required) f s1 f s2 17.734475 35.468950 mhz mhz xt0 and xt1 inputs cycle time high time low time 1 2 3 28.2 12 12 ns ns ns clkx1 duty cycle clkx2 duty cycle clkx2 to clkx1 delay clkx1 to data delay clkx2 to data delay 8-bit mode: data to qclk (rising edge) delay qclk (rising edge) to data delay 16-bit mode: data to qclk (rising edge) delay qclk (rising edge) to data delay 4 5 6 7a 8a 7b 8b 45 40 1 5 8 5 15 15 25 55 60 8 20 20 % % ns ns ns ns ns ns ns
93 p arametric i nformation ac electrical parameters bt819a/7a/5a figure 37. clock timing diagram xt0i clk x 2 or xt1i clk x 1 p ixel and c ontrol d ata 1 2 3 4 6 5 qclk p ixel and c ontrol d ata qclk 8 b 7 b 8 a 7 a 16-b it m ode 8-b it m ode
94 p arametric i nformation ac electrical parameters bt819a/7a/5a table 18. power supply current parameters parameter symbol min typ max units supply current (bt819a and bt817a) v aa =v dd =5.0v, f clkx2 =28.64 mhz, t=25?c v aa =v dd =5.25v, f clkx2 =35.47 mhz, t=70?c v aa =v dd =5.25v, f clkx2 =35.47 mhz, t=0?c supply current, power down i 230 100 310 340 ma ma ma ma supply current (bt815a) v aa =v dd =5.0v, f clkx2 =28.64 mhz, t=25?c v aa =v dd =5.25v, f clkx2 =35.47 mhz, t=70?c v aa =v dd =5.25v, f clkx2 =35.47 mhz, t=0?c supply current, power down i 230 100 265 285 ma ma ma ma table 19. output enable timing parameters parameter symbol min typ max units oe asserted to data bus driven oe asserted to data valid oe negated to data bus not driven 9 10 11 0 100 100 ns ns ns rst low time 8 xtal cycles figure 38. output enable timing diagram oe 10 11 p ixel , c lock and c ontrol d ata 9
95 p arametric i nformation ac electrical parameters bt819a/7a/5a table 20. jtag timing parameters parameter symbol min typ max units tms, tdi setup time tms, tdi hold time tck asserted to tdo valid tck asserted to tdo driven tck negated to tdo three-stated tck low time tck high time 12 13 14 15 16 17 18 25 25 10 10 60 5 80 ns ns ns ns ns ns ns figure 39. jtag timing diagram 12 13 17 18 14 15 16 tdi, tms tck tdo
96 p arametric i nformation ac electrical parameters bt819a/7a/5a note: test conditions (unless otherwise speci?d): ?ecommended operating condi- tions.?ttl input values are 0? v, with input rise/fall times 3 ns, measured be- tween the 10% and 90% points. timing reference points at 50% for digital inputs and outputs. pixel and control data loads 30 pf and 3 10 pf. clkx1 and clkx2 loads 50 pf. control data includes cbflag, dvalid, active, hreset , vreset and field table 21. fifo timing parameters (bt819a only) parameter symbol min typ max units frst low time clkin rate clkin duty cycle rden setup time rden hold time clkin to data delay (except dvalid) fifo data retention time data to qclk (rising edge) delay qclk (rising edge) to data delay clkin to dvalid data delay 19 20 21 22 23 24 4 40 10 5 5 64 10 6 5 36 60 20 22 clkx1 cycles mhz % ns ns ns ms ns ns ns figure 40. fifo output timing diagram 21 20 23 22 19 clkin rden p ixel and c ontrol d ata qclk valid valid 24 table 22. decoder performance parameters parameter symbol min typ max units horizontal lock range 7 % of line length fsc, lock-in range 800 hz gain range ? 6 db
97 p arametric i nformation package mechanical drawings bt819a/7a/5a package mechanical drawings figure 41. 100pqfp package mechanical drawing
98 p arametric i nformation package mechanical drawings bt819a/7a/5a figure 42. 100tqfp package mechanical drawing
99 p arametric i nformation datasheet revision history bt819a/7a/5a datasheet revision history table 23. bt819a datasheet revision history (1 of 2) revision date change description rev. a 4/21/95 corrections from l819001 rev. b 1) description of bytestream changed to indicate clkx2 is normally used and not qclk. 2) the recommended inductor value in the anti-aliasing ?ter in ?ypi- cal external circuitry changed to 3.3 m h from 3.6 m h. note the recommended tolerance for all inductors in the datasheet is 10% 3) figure 26 changed to indicate that pixel output data changes one clock after dvalid transitions low. 4) table 9 changed to indicate that hreset is output after the last pixel in a line and vreset is output after the hreset of the last line in the ?ld. 5) typographical mistake in the recommended entry for the hscale_lo value at the beginning of the control register de?i- tion section. the value for square pixel ntsc was changed from 0xac to 0xaa. 6) the power numbers have been added to table 18 for all three devices. 7) suggested con?uration for use of the fifo in api mode b has been added to the api section of the datasheet.
100 p arametric i nformation datasheet revision history bt819a/7a/5a rev. b 12/29/95 1) bt815 pin de?itions changed to provide complete compatibility between bt819, bt817 and bt815 (pin numbers 64, 67, 74 and 81). 2) bt817 pin de?ition for pin 81 changed to provide compatibility between bt819, bt817 and bt815. 3) standard crystal included in recommended crystal manufacturers as they offer very short lead times. 4) bias capacitors changed to optional. not recommended for new designs. 5) fifo pin de?itions in table 7 and table 9 are incorrect. the even ?ld is ?ld 2, and the odd ?ld is ?ld 1. 6) api mode-a change: clkin must be connected to clkx1. 7) api mode-b change: the fifo should not be emptied while active video is being written into the fifo. do not read the fifo until empty, during the active video line. 8) in both api modes a and b: the control codes are not valid when the fifo is not being read. 9) example schematic in figure 36 changed to re?ct bt819a. 10) typographical error in the status register corrected. cof is the least signi?ant bit. 11) additional crystal vendors added. short lead times available from standard crystal. 12) the timing from qclk to data valid in 8-bit mode was changed. see figure 37. 13) the vpole register de?ition was changed to indicate that dvalid, field and aff do not have programmable polarities in api mode. rev. c 09/18/96 in functional description section under scaling registers, hscale: was = 12331 changed to = 15602 table 23. bt819a datasheet revision history (2 of 2) revision date change description
rockwell semiconductor systems, inc. 9868 scranton road san diego, ca 92121-3707 (619) 452-7580 1(800) 2-bt-apps fax: (619) 452-1249 internet: image@brooktree.com l819_c printed on recycled paper

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